Since OCR value is changed,1ms delay is added to
give cards time to respond.
Change-Id: I18bddbc9d01ab2c62529c9f2065331f83b7ecca9
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
As 52Mhz clk does not have 50% dutycycle, setting
48MHz clk for mmc data transfer mode
Change-Id: Id9c0ce07fe652df7d575c5ea11f1d83eab0fb24c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
fdt_path_offset function will return zero or positive
value for success case.So fixed the return value check
accordingly.
Change-Id: Iafacdaf7c12cecdb882f3795f6145730efe938a6
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Do generic flash structure initialization, for the devices
not listed in the SPI NOR flash lookup table, so that
we can access the flash even before the support is added.
Block size and density are obtained from smem.
Change-Id: I568eb538615bb36124c43a2509bcfce2e4a1188a
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
This patch will improve the spi flash read/write
performance.
Change-Id: I3939d202bf504a3386a4ae44644c715ec17f01ab
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
Changed the assert and deassert sequence to enable the pcie
linkup for peripheral specific devices.
Change-Id: I2f93f818fe9f85ffa43fb5dff1a9cc67ae393183
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
When 4K sector size support is enabled for spi, always
4K sector erase command is passed for all the erase operations.
To increase the performance, 64K erase command is
passed to the command buffer based on length and offset.
Change-Id: Ia762d192ba5d424f0ba3538fff8aff4954050bf7
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
Adding nullpointer condition checks before the pointer
is accessed or passed to a function as argument.
Change-Id: I6848c132076708f69fad00a75e42a1c2f33b6215
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
With specific USB storage device, usb start command causing
system reboot. This change avoids queuing any new URB on a
halted endpoint.
The failure log is given below:
------------------------ ERROR MESSAGE ---------------------------
scanning bus 1 for devices...
WARN halted endpoint, queueing URB anyway.
Unexpected XHCI event TRB, skipping... (87244c70 00000000 13000000 01008401)
BUG: failure at drivers/usb/host/xhci-ring.c:489/abort_td()!
BUG!
------------------------------------------------------------------
Change-Id: I0735b89832416ebd4b8d80129572afec4bb950a4
Signed-off-by: Pradeep Das <pkdas@codeaurora.org>
This change is ported based on commit b83c56c4d4
Change-Id: Ia4cdf26368d238ea3fcdb808f1446f010408a78c
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
During usb start, all the hub initialization happens,
before scanning the bus for devices. In DK, bus 0 has
2 NbrPorts and bus 1 has 1 NbrPorts. Since there are
two ports(USB0 and USB1) available, such initialization
overwrites the NbrPorts of the hub descriptor. Hence it
fails to detect the USB 3.0.
This patch modifies the logic to scan for devices in the
hub before initializing the next hub.
Change-Id: I1071d7c38a896864fe15d8b07bdb2a84ddcac7bf
Signed-off-by: Sasirekaa Madhesu <smadhesu@codeaurora.org>
SPI flash is disabled in DK07-C2, C3 boards. If the
controller tries to probe spi flash, it will wait
indefinitely for response from slave and the
board hangs.
Hence added a maximum timeout of 2 seconds instead
of waiting on a infinte loop for the BAM interrupt
to trigger.
Change-Id: Iabb88352d87e2db756c557e424d64a40c7780310
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sasirekaa Madhesu <smadhesu@codeaurora.org>
This patch makes mmc driver dcache aware to keep
the mmc functionality intact, with or without dcache
is enabled.
flush_cache used here does both clean and invalidate
cache thus preventing data loss during unaligned access,
if any.
Change-Id: I0910bd17678d3855bba27e9f8f7c08606774b28d
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This patch adds the support on nand driver to work
when dcache is on.
flush_dcache_range will do both clean and invalidate.
To avoid any data loss when an un-aligned buffer used
in RX path, before giving buffer to bam and after bam
updates the data in buffer, buffer will be flushed.
Change-Id: Ib38d68726efe1692ae94c2be1af61cf29d1c2e50
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, ipq
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: I5a80cd371a926efa36c40b4db68e78ed78c30536
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation
1. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
2. The read should return the complete data in case of
EBADMSG so move the EBADMSG check in the main read function.
Change-Id: Iab3a28427e8350e8c99368762373f2cbce918786
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. assign ecc strength in mtd structure which will be used by
mtd layer
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: I81cfe6059375117ced7888b877705919287a7be2
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. Added pci entries in AP160 and AP160_2xx dts
2. The wifi pcie card requires to be powered on from GPIO
pins. This patch also adds the same in AP160 dts file and
enable it during PCIe configuration.
Change-Id: Icd8f5741d5df38d46640c78a7475853e77b873a9
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
