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ipq806x: set 48MHz clk for mmc data transfer mode

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As 52Mhz clk does not have 50% dutycycle, setting
48MHz clk for mmc data transfer mode

Change-Id: Id9c0ce07fe652df7d575c5ea11f1d83eab0fb24c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This commit is contained in:
Rajkumar Ayyasamy 2018-03-19 11:47:02 +05:30
parent 7bb2910d6a
commit 14fe9facff
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/ipq806x_clk.c
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@ -600,10 +600,10 @@ void emmc_clock_config(int mode)
udelay(10);
}
if (mode == MMC_DATA_TRANSFER_MODE) {
/*52 MHz pll8 */
emmc_set_rate_mnd(13, 32);
/*48 MHz pll8 */
emmc_set_rate_mnd(1, 8);
emmc_pll_vote_clk_enable();
emmc_local_clock_enable(13, 32, 3, 3, 3);
emmc_local_clock_enable(1, 8, 1, 3, 3);
emmc_clock_reset();
udelay(10);
}