1. Added pci entries in AP160 and AP160_2xx dts
2. The wifi pcie card requires to be powered on from GPIO
pins. This patch also adds the same in AP160 dts file and
enable it during PCIe configuration.
Change-Id: Icd8f5741d5df38d46640c78a7475853e77b873a9
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This patch fixes the erase timeout issue in emmc.
Change-Id: I35031d834fda4ee7560e84787e18e8bc0a3f28fe
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This command helps to debug the phy issues.
Change-Id: If8354d6826795d9ef9d44112582d3b911963bda5
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This patch fixes the issues in below i2c commands.
i2c probe , i2c md and i2c mw commands.
Change-Id: I3dd99e8846452b20a71b0664d325b309f3564579
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This patch enables SPI-NAND support for DK and making
chip select gpio configurable from DTS.
Change-Id: I2ca7d3021fa27da1d83e2a787a1dc626919124f8
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Enabling spi dma driver for ipq40xx. This patch
also enables rx and tx pipe configurable from dts.
Change-Id: Id6009f6e9863ab2cdf8b105461d62aa68e3d004b
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Enable the PPE tx_mac only if the phy link is up else disble
the PPE tx_mac.
Change-Id: I7226a104fa287f8378b98923a00d0caa3f91079d
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This is a snapshot of the spi_nand as of uboot-1.0
commit:
e6434d80905a219860c8ede78377221ded2510f2 (ipq40xx:
Add bit-flip threshold for QPIC NAND)
Change-Id: I91db5822cc450e9d7eb52fca9eab213784547206
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
1. This driver is directly being registered with MTD
layer.So for OOB operations, the device OOB size will be
passed. NAND controller can’t handle the complete OOB so
calculate NAND Controller supported OOB size and overwrite
the device OOB size with that.
2. Enabling 8 bit ECC support in dev0_ecc_cfg register
Change-Id: I5f4297932eea6bed47182d235d081cbe30d1b85c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
using nand command will change the default nand device to 1. This will
try to read the nor patitions so one if user tries to read the nand partitions.
Change-Id: Id73e89f479b5735fd5b28a871680190f48a76f0e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
The erase timeout has been calculated using the
EXT_CSD_TRIM_MULT so that the erase operation with
larger block counts are not affected.
Change-Id: Ia6dd9318c44b4da315c2b2a82cfabe9eff0aeb41
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
As DK and AK does not have pci-phy entry making it as
applicable only for HK
Change-Id: I52d110f4012b867bb019859be9168b3aea68bfd4
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
SGMII channel 0 is used for uniphy instance 1 and 2,
so set the SG_MODE for uniphy instance 1 and 2. Channel 0,1
and 4 are used for instance 0. So set CH1_CH0_SGMII and
CH4_CH1_0_SGMII for channel 1 and 4 respectively.
Change-Id: Ie6f0afa6419a9895f730c89fa27fb80b122acf73
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, qpic
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: Ie0427c6802e2e41234137e0fbbf51c5a50a35946
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This patch does minor code reorganization to store spare, ecc and
bbm bytes in nand device structure which will be useful in
subsequent patches.
Change-Id: Id44c53e204a874569968764798c346a609695acf
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation for
checking the read errors
1. For checking the erased CW, NAND_ERASED_CW_DETECT_STATUS
is being read inside qpic_nand_check_status. The
qpic_nand_check_status will be called after complete page read
so reading status register won’t help in getting the register
value after each CW reads.
2. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
3. mtd->ecc_stats is only applicable when ECC engine is
doing ECC correction. For raw reads, the stats should not be
incremented.
Now the changes have been done to reorganize the error handling
1. schedule the NAND_ERASED_CW_DETECT_STATUS reading after
every CW read and check the same if ECC engine generates
uncorrectable error.
2. For raw read, the ECC engine will never generate the
uncorrectable error or erased CW so check only
NAND_FLASH_STATUS.
3. The qpic_nand_read_oob should return the maximum number
of bitflips that were corrected on any one ecc region so
introduce the max_bitflips for maintaining the same.
4. The read should return the complete data in case of
BADMSG so move the BADMSG check in the main read function.
Change-Id: Ibef56294ace00d7cd67b501f623fb1d3aeb2c6ec
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. ecc strength can be assigned in mtd structure itself so
remove the ecc_width from qpic nand dev structure
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: Ieafd1957b89a05f9dd0fdfe829712d8891bd6a48
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
NANDC_RESULT_BAD_PAGE is not being returned by any operation, so
it can be removed.
Change-Id: Ia90e4e6b7ef7577d069d312d51083b50f49bf980
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This patch enables SDHCI mode and also supports
data transfer using ADMA method.
Change-Id: Ia3187fec9024ad0972ca720cf0b9ddc6a59b906c
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Reset command must be the first command issued to all
targets after the NAND flash device is powered on.
Change-Id: I617dc5b0ad8d72705dcf20f1cb554134b166e533
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
