Some cards are not working due to pcie reset.
So doing pcie reset with pcie reset gpio.
Change-Id: I0c631b116923b90bf94223d09e5662900a31244e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
TX and RX descriptors are 16 bytes. This causes problems with the cache
maintenance on CPUs where the cache-line size exceeds the size of these
descriptors. What will happen is that when the driver receives a packet
it will be immediately requeued for the hardware to reuse. The CPU will
therefore need to flush the cache-line containing the descriptor, which
will cause all other descriptors in the same cache-line to be flushed
along with it. If one of those descriptors had been written to by the
device those changes (and the associated packet) will be lost.
To work around this, we make use of non-cached memory if available. If
descriptors are mapped uncached there's no need to manually flush them
or invalidate them.
Change-Id: I7b8a9a55226dfdcbab49a93bcdf43af4d70c108a
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This change enables u-boot support for AP.DK07.1-C4 configuration.
AP.DK07.1-C4 enables QCA402x IOT support
Change-Id: I5982b8f8783755b03d11c878f8108d71e6ace6d1
Signed-off-by: Gitanjali Krishna <gitanjal@codeaurora.org>
Currently, the nand driver expects the start address to be page
aligned. This patch adds the support for reading data from
non-page aligned start address by using intermediate buffer.
1. Determine the number of pages with start address and
length.
2. Do the full page read for all the pages. For first page,
check the start address and determine the column. If column is
non-zero then use the intermediate buffer for page data and copy
the required number of bytes from this intermediate buffer to
actual buffer.
Change-Id: I05a4b98547c83f785096027596cedd83a283edd8
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
eMMC part THGBMBG5D1KBAIT is taking long time for the secure trim.
This leads to erase timeout. Manufacturer ID based quirk is added
for the specific part to use trim instead of secure trim for block erase.
Change-Id: Id4ecfde9585e112521863439f684feb5e0caaa51
Signed-off-by: Vinoth Gnanasekaran <vgnana@codeaurora.org>
xHCI spec says: the values of the 'route string' field shall be
initialized by the first 'Address Device' command issued to a
device slot, and shall not be modified by any other command.
So far U-Boot does not program this field, and it does not prevent
SS device directly attached to root port, or HS device behind an HS
hub, from working, due to the fact that 'route string' is used by
the xHC to target SS packets. But in order to enumerate devices
behind an SS hub, this field must be programmed.
With this commit and along with previous commits, now SS & HS devices
attached to a USB 3.0 hub can be enumerated by U-Boot.
As usual, this new feature is only available when DM is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit 493b8dd070)
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Change-Id: I367a0f1fa5e310c1c6af2d4675a86a3293337d64
For future extension, change xhci_setup_addressable_virt_dev()
signature to accept a pointer to 'struct usb_device', instead
of its members slot_id & speed, as the struct already contains
these two plus some other useful information of the device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit daec469144)
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Change-Id: Ibd7991073f0de4a97babbd9a96270f53f77cb185
Use USB hub device's dev->uclass_priv to point to 'usb_hub_device'
so that with driver model usb_hub_reset() and usb_hub_allocate()
are no longer needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit dfa96e0676)
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Conflicts:
common/usb_hub.c
Change-Id: I7a46a12c62aa7429ef2241c9543dd877abe6ac0b
Sometimes we need know if a given hub device is root hub or not.
Add a new API to test this. This removes the xHCI driver's own
version is_root_hub() and change to use the new API.
While we are here, remove the unused/commented out get_usb_device()
in the xHCI driver too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
(cherry picked from commit 46c1d49330)
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Change-Id: Ia27ee3b541f936e3eebf6ecb57c3499c08da3781
USB 3.0 hubs have a slightly different hub descriptor than USB 2.0
hubs, with a fixed (rather than variable length) size. Change the
host controller drivers that access those last two fields
(DeviceRemovable and PortPowerCtrlMask) to use the union.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
(cherry picked from commit 337fc7e665)
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Change-Id: I4ee4c866f4d35fea3ecf6431b90cec1af121fe29
Testing a USB 3.0 hub by connecting it to the xHCI port on Intel
MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI
reports a transfer event TRB with a completion code 6 which means
'Stall Error'.
In fact super speed USB hub descriptor type is 0x2a, not 0x29.
Sending correct SETUP packet to the hub makes it not stall anymore.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
(cherry picked from commit f342119602)
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Change-Id: I105e81557ec4097e6fafafdd2e2b5ecffb75b56b
eMMC part SDIN8DE1-8G is taking long time for the secure trim.
This leads to erase timeout. Manufacturer ID based quirk is added
for the specific part to use trim instead of secure trim for block erase.
Change-Id: I13d5a9f19edf5daf9c1f4d5c2ec16b4f3b680159
Signed-off-by: Pradeep Das <pkdas@codeaurora.org>
Currently NAND_CTRL register write generates error.
Register writes to operational registers should always be done
through command descriptors if BAM_MODE is already enabled.
For NAND boot, bootloader already enables BAM_MODE so read the
NAND_CTRL register value and write only if BAM_MODE is not set.
Change-Id: Iabc3e06dc7d8d8b36cdf35907217e1c4d7cc960a
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
If nand id table has specified oobsize then use the same.
Change-Id: I58b19f8f9989c7332d103b83b6920d5b59b29a13
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following error is coming during UBI mount for non ONFI nand
device since mtd->writebufsize is coming as zero
ubi0: attaching mtd2
UBI init error 22
The mtd->writebufsize is being assigned currently for ONFI
devices only so move this assigment to common place.
Change-Id: Idd22800dd65035952c1afd07ba375a28ffcf76ad
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The ONFI NAND device specifies the required ECC correction in its
param page but for non ONFI device, we don't have such info.
The QPIC NAND contoller can use 8 bit ECC if the chip has required
number of spare bytes. This patch calculates the minimum required
spare bytes for using 8 bit ECC and select the same, if non ONFI
device has required number of spare bytes otherwise 4 bit ECC
will be used.
Change-Id: If7c718f4288eee16857171335897e3209a05fd0b
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Add the full description of the Toshiba TH58NYG3S0H NAND chip
in the nand_ids table since its spare bytes are coming as 128
instead of 256 with standard calculation. This device is non
ONFI/JEDEC device.
Change-Id: If1938fbcd0ebceb70aa9b620186cc92c6d504f75
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. Added emmc clk reset during mmc deinitialization to
avoid the mmc init failure in kernal bootup.
2. Clock has been configured to 192 Mhz for SDHCI mode
3. Proper register is used for disabling emmc clock
Change-Id: Id21e294380ee904027e5d6d2b2929acbd7bac672
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Software SPI reset mode can be trigger from 4-Byte Address mode
in flash W25Q256JW.
Change-Id: I3f8ec46c2732c07a7af0cc7331102334413067ba
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Since OCR value is changed,1ms delay is added to
give cards time to respond.
Change-Id: I18bddbc9d01ab2c62529c9f2065331f83b7ecca9
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
As 52Mhz clk does not have 50% dutycycle, setting
48MHz clk for mmc data transfer mode
Change-Id: Id9c0ce07fe652df7d575c5ea11f1d83eab0fb24c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
fdt_path_offset function will return zero or positive
value for success case.So fixed the return value check
accordingly.
Change-Id: Iafacdaf7c12cecdb882f3795f6145730efe938a6
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Do generic flash structure initialization, for the devices
not listed in the SPI NOR flash lookup table, so that
we can access the flash even before the support is added.
Block size and density are obtained from smem.
Change-Id: I568eb538615bb36124c43a2509bcfce2e4a1188a
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
This patch will improve the spi flash read/write
performance.
Change-Id: I3939d202bf504a3386a4ae44644c715ec17f01ab
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
