After reading data from mmc, dest pointer will point to
the end address. To calculate the start of dest pointer
number of bytes copied has to be subtracted.
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I24610a3b3bb498c4ee4ebba58e557d109c6af1ef
This eMMC flash controller support only 4-bit
Update sdhci driver to support 4-bit mode.
Change-Id: Iddaa0807b7cf339fcfa5add0b96955757b33c716
Signed-off-by: Vandhiadevan <vkarunam@codeaurora.org>
As per the SD controller hardware design document
the SD bus power should be turned off and the iopad
voltage has to be set to 3V (default), before
doing reset for all in SD host controller.
Change-Id: Ia77bb0acefe1e619c8ae7a2bc60024bf1ac5c6cd
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
moving __weak function from board specific file to
common file to avoid implicit declaration of function
warning
Change-Id: I60232c24eb3f7c4e16831de16452def3fe2671c3
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
eMMC part THGBMNG5D1LBAIT (Toshiba 4GB) is taking long time for
the secure trim.This leads to erase timeout. Manufacturer ID based
quirk is added for the specific part to use trim instead of secure
trim for block erase.
without this change we can see the error erase timeout and erase failed.
error:
MMC erase: dev # 0, block # 6690, count 2047 ... sdhci_send_command:
MMC: 0 busy timeout increasing to: 2000 ms.
sdhci_send_command: MMC: 0 busy timeout increasing to: 4000 ms.
timeout.
mmc erase failed
-1 blocks erased: ERROR
Change-Id: I1126690400b274bb4735750584d7fb4b105e6618
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will handle masking of DAT inhibit bit of
present state register. This status bit is genarated if
either the DAT Line Active or Read Transfer Active is set to
1. If this bit is 0, it indicates the host controller can issue
the next command.
Commands with busy signal belong to Command Inhibit(DAT).
e.g (R1b, R5b type).
Changing from 1 to 0 generates a transfer complete interrupt
in normal interrupt status register.
If this bit value is 1: Cannot issue command which uses DAT line.
If this bit value is 0: Can issue command which uses DAT line.
This change is masking SDHCI_DATA_INHIBIT bit only if card is in
busy state.
Without this change we can get the erase timeout error.
error:
MMC erase: dev # 0, block # 27682, count 16383 ...
sdhci_send_command: MMC: 0 busy timeout increasing to: 2000 ms.
Change-Id: I0612e576c09a7fd077bed1a1ee717afcddfa7e87
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change is a workaround for Micron eMMC card. As per the card
extended CSD register value, the minimum size of a write protect
region is 0x8000 blocks (16MB). So the user should give start address
and size to align with 0x8000. But this eMMC part actually does
protect 32MB of memory.
We changing the minimum write protect region size from 0x8000 to
0x10000 for Micron eMMC card.
Change-Id: Id53c337374dfba8adb6bd550826337d8ecfe17f3
Signed-off-by: Vinoth Gnanasekaran <vgnana@codeaurora.org>
The Device will accept the requested number of data blocks, terminate
the transaction and return to transfer state. Stop command is not
required at the end of this type of multiple blocks write unless
terminated with an error. This change will send the
STOP_TRANIMISSION command if the command failed.
Change-Id: I9bd419ab8931d80a4a2eeba9f5bd42222257a824
Signed-off-by: Vinoth Gnanasekaran <vgnana@codeaurora.org>
This patch checks for the errors during the fifo write itself
like in qca_pio_read function. Previously, error was checked
only after the total xfer_size is written to the fifo and
errors during the fifo write operation were ignored.
Change-Id: I2a549b0032bfd774973773cc49b595c75682aac7
Signed-off-by: Balaji Prakash Jagadeesan <bjagadee@codeaurora.org>
We are allocating the dma descriptors,but they are not explicitly
freed. This change will free the dma descriptors after every transfer.
Change-Id: I0a851923ab4d2551215e29b34c7c31b85502fb3f
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
eMMC part THGBMBG5D1KBAIT is taking long time for the secure trim.
This leads to erase timeout. Manufacturer ID based quirk is added
for the specific part to use trim instead of secure trim for block erase.
Change-Id: Id4ecfde9585e112521863439f684feb5e0caaa51
Signed-off-by: Vinoth Gnanasekaran <vgnana@codeaurora.org>
eMMC part SDIN8DE1-8G is taking long time for the secure trim.
This leads to erase timeout. Manufacturer ID based quirk is added
for the specific part to use trim instead of secure trim for block erase.
Change-Id: I13d5a9f19edf5daf9c1f4d5c2ec16b4f3b680159
Signed-off-by: Pradeep Das <pkdas@codeaurora.org>
Since OCR value is changed,1ms delay is added to
give cards time to respond.
Change-Id: I18bddbc9d01ab2c62529c9f2065331f83b7ecca9
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
Adding nullpointer condition checks before the pointer
is accessed or passed to a function as argument.
Change-Id: I6848c132076708f69fad00a75e42a1c2f33b6215
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
This patch makes mmc driver dcache aware to keep
the mmc functionality intact, with or without dcache
is enabled.
flush_cache used here does both clean and invalidate
cache thus preventing data loss during unaligned access,
if any.
Change-Id: I0910bd17678d3855bba27e9f8f7c08606774b28d
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This patch fixes the erase timeout issue in emmc.
Change-Id: I35031d834fda4ee7560e84787e18e8bc0a3f28fe
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
The erase timeout has been calculated using the
EXT_CSD_TRIM_MULT so that the erase operation with
larger block counts are not affected.
Change-Id: Ia6dd9318c44b4da315c2b2a82cfabe9eff0aeb41
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This patch enables SDHCI mode and also supports
data transfer using ADMA method.
Change-Id: Ia3187fec9024ad0972ca720cf0b9ddc6a59b906c
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
This patch enables qca_mmc driver and
also has the changes required for emmc
support
Change-Id: Icc8d807caffced79d6ca576fe6220c522ebda3f7
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
As the U-boot source is going to be common between ARM and MIPS
architecture , it is required to pick only the files specific
to the respective architectures during the build.
So, move the qca arm target specific common files to another
sub level by specifying the ARCH arm.
Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
This fix removes the mmc_init that is being called during
board init to prevent error message in cases where eMMC
card is not connected.
Change-Id: I918c71c391002d24e704be30043ff0cc8dfd4f83
Signed-off-by: G Dhivya <gdhivya@codeaurora.org>
Fixed warnings for both ipq807x and ipq40xx
builds.
Change-Id: I69accebf525ee52f470335a14474378f5e7f65b0
Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
This patch has the initial changes required to make the
qca_mmc driver buildable. Also added the Kconfig
options required for the qca_mmc driver.
Change-Id: I15c0e9288ae5c7ae361659dff1e84b619de989a8
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Table 41 of the JEDEC standard for eMMC says that bit 31 of
the command argument is obsolete when issuing the ERASE
command (CMD38) on page 115 of this document:
http://www.jedec.org/sites/default/files/docs/jesd84-B45.pdf
The SD Card Association Physical Layer Simplified Specification also
makes no mention of the use of bit 31.
https://www.sdcard.org/downloads/pls/part1_410.pdf
The Linux kernel distinguishes between secure (bit 31 set) and
non-secure erase, and this patch copies the macro names from
include/linux/mmc/core.h.
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Eric Nelson <eric@nelint.com>
Tested-by: Hector Palacios <hector.palacios@digi.com>
The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.
Guard against their usage by hiding the bit mask macros on those
processors.
These bits are used to prevent glitches when changing clocks on
i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.
>From the i.MX6DQ RM:
To prevent possible glitch on the card clock, clear the
FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
or DVS in System Control Register) or setting RSTA bit.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Hector Palacios <hector.palacios@digi.com>
Move the macro into the socfpga_dwmci_clksel().
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
[fix parenthesis in the sdmmc_mask]
There is no sprintf implementation in tiny-printf, so don't try to use
it when tiny-printf if used.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Calculate the minimum sd clock based on max clock. This will
be done by add_sdhci() if we pass minimum clock as zero.
It also does based on SD host contoller version.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Convert the SoCFPGA shim for registering the DWMMC driver to DM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
