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synced 2025-12-10 07:44:53 +01:00
ipq807x: mmc: Added eMMC driver files
Change-Id: Icf1683ebe1c7e99c336d884983215d7b416c988b Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
This commit is contained in:
Vasudevan Murugesan
parent
df62dea585
commit
a07af4aa36
2 changed files with 439 additions and 0 deletions
321
drivers/mmc/qca_mmc.c
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321
drivers/mmc/qca_mmc.c
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/*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <mmc.h>
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#include <part.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch-qcom-common/clk.h>
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#include <asm-generic/errno.h>
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#include "../../board/qcom/common/qca_common.h"
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#include "qca_mmc.h"
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static inline void qca_reg_wr_delay(qca_mmc *host)
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{
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while (readl(host->base + MCI_STATUS2) & MCI_MCLK_REG_WR_ACTIVE);
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}
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static inline void
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qca_start_command_exec(qca_mmc *host, struct mmc_cmd *cmd)
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{
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unsigned int c = 0;
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unsigned int arg = cmd->cmdarg;
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writel(MCI_CLEAR_STATIC_MASK, host->base + MMCICLEAR);
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qca_reg_wr_delay(host);
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c |= (cmd->cmdidx | MCI_CPSM_ENABLE);
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136)
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c |= MCI_CPSM_LONGRSP;
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c |= MCI_CPSM_RESPONSE;
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}
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if ((cmd->resp_type & MMC_RSP_R1b) == MMC_RSP_R1b) {
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c |= MCI_CPSM_PROGENA;
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}
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writel(arg, host->base + MMCIARGUMENT);
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writel(c, host->base + MMCICOMMAND);
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qca_reg_wr_delay(host);
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}
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static int
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qca_start_command(qca_mmc *host, struct mmc_cmd *cmd)
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{
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unsigned int status = 0;
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int rc = 0;
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qca_start_command_exec(host, cmd);
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while (readl(host->base + MMCISTATUS) & MCI_CMDACTIVE);
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status = readl(host->base + MMCISTATUS);
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if ((cmd->resp_type != MMC_RSP_NONE)) {
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if (status & MCI_CMDTIMEOUT) {
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rc = TIMEOUT;
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}
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/* MMC_CMD_SEND_OP_COND response doesn't have CRC. */
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if ((status & MCI_CMDCRCFAIL) && (cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
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rc = UNUSABLE_ERR;
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}
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cmd->response[0] = readl(host->base + MMCIRESPONSE0);
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/*
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* Read rest of the response registers only if
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* long response is expected for this command
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*/
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[1] = readl(host->base + MMCIRESPONSE1);
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cmd->response[2] = readl(host->base + MMCIRESPONSE2);
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cmd->response[3] = readl(host->base + MMCIRESPONSE3);
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}
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}
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writel(MCI_CLEAR_STATIC_MASK, host->base + MMCICLEAR);
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qca_reg_wr_delay(host);
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return rc;
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}
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static int
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qca_pio_read(qca_mmc *host, char *buffer, unsigned int remain)
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{
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unsigned int *ptr = (unsigned int *) buffer;
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unsigned int status = 0;
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unsigned int count = 0;
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unsigned int error = MCI_DATACRCFAIL | MCI_DATATIMEOUT | MCI_RXOVERRUN;
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unsigned int i;
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do {
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status = readl(host->base + MMCISTATUS);
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udelay(1);
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if (status & error) {
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break;
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}
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if (status & MCI_RXDATAAVLBL ) {
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unsigned rd_cnt = 1;
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if (status & MCI_RXFIFOHALFFULL) {
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rd_cnt = MCI_HFIFO_COUNT;
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}
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for (i = 0; i < rd_cnt; i++) {
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*ptr = readl(host->base + MMCIFIFO +
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(count % MCI_FIFOSIZE));
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ptr++;
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count += sizeof(unsigned int);
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}
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if (count == remain)
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break;
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} else if (status & MCI_DATAEND) {
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break;
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}
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} while (1);
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return count;
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}
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static int
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qca_pio_write(qca_mmc *host, const char *buffer,
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unsigned int remain)
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{
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unsigned int *ptr = (unsigned int *) buffer;
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unsigned int status = 0;
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unsigned int count = 0;
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unsigned int error = MCI_DATACRCFAIL | MCI_DATATIMEOUT | MCI_TXUNDERRUN;
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unsigned int bcnt = 0;
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unsigned int sz = 0;
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int i;
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do {
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status = readl(host->base + MMCISTATUS);
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bcnt = remain - count;
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if (!bcnt)
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break;
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if ((status & MCI_TXFIFOEMPTY) ||
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(status & MCI_TXFIFOHALFEMPTY)) {
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sz = ((bcnt >> 2) > MCI_HFIFO_COUNT) \
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? MCI_HFIFO_COUNT : (bcnt >> 2);
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for (i = 0; i < sz; i++) {
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writel(*ptr, host->base + MMCIFIFO);
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ptr++;
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count += sizeof(unsigned int);
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}
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}
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} while (1);
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do {
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status = readl(host->base + MMCISTATUS);
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if (status & error) {
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count = status;
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break;
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}
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} while (!(status & MCI_DATAEND));
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return count;
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}
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static int
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qca_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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unsigned int datactrl = 0;
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qca_mmc *host = mmc->priv;
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unsigned int xfer_size ;
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int status = 0;
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if (data) {
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writel((readl(host->base + MMCICLOCK) | MCI_CLK_FLOWENA),
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host->base + MMCICLOCK);
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xfer_size = data->blocksize * data->blocks;
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datactrl = MCI_DPSM_ENABLE | (data->blocksize << 4);
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writel(0xffffffff, host->base + MMCIDATATIMER);
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if (data->flags & MMC_DATA_READ)
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datactrl |= (MCI_DPSM_DIRECTION | MCI_RX_DATA_PEND);
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writel(xfer_size, host->base + MMCIDATALENGTH);
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writel(datactrl, host->base + MMCIDATACTRL);
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qca_reg_wr_delay(host);
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status = qca_start_command(host, cmd);
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if (data->flags & MMC_DATA_READ) {
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qca_pio_read(host, data->dest, xfer_size);
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} else {
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qca_pio_write(host, data->src, xfer_size);
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}
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writel(0, host->base + MMCIDATACTRL);
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qca_reg_wr_delay(host);
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} else if (cmd) {
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status = qca_start_command(host, cmd);
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}
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return status;
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}
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void qca_set_ios(struct mmc *mmc)
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{
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qca_mmc *host = mmc->priv;
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u32 clk = 0, pwr = 0;
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int mode;
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if (mmc->clock <= mmc->f_min) {
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mode = MMC_IDENTIFY_MODE;
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} else {
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mode = MMC_DATA_TRANSFER_MODE;
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}
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if (mode != host->clk_mode) {
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host->clk_mode = mode;
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emmc_clock_config(host->clk_mode);
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}
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pwr = MCI_PWR_UP | MCI_PWR_ON;
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writel(pwr, host->base + MMCIPOWER);
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qca_reg_wr_delay(host);
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clk = readl(host->base + MMCICLOCK);
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clk |= MCI_CLK_ENABLE;
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clk |= MCI_CLK_SELECTIN;
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clk |= MCI_CLK_FLOWENA;
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/* feedback clock */
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clk |= (2 << 14);
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if (mmc->bus_width == 1) {
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clk |= MCI_CLK_WIDEBUS_1;
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} else if (mmc->bus_width == 4) {
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clk |= MCI_CLK_WIDEBUS_4;
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} else if (mmc->bus_width == 8) {
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clk |= MCI_CLK_WIDEBUS_8;
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}
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/* Select free running MCLK as input clock of cm_dll_sdc4 */
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clk |= (2 << 23);
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/* Don't write into registers if clocks are disabled */
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writel(clk, host->base + MMCICLOCK);
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qca_reg_wr_delay(host);
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writel((readl(host->base + MMCICLOCK) | MCI_CLK_PWRSAVE), host->base + MMCICLOCK);
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qca_reg_wr_delay(host);
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}
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int qca_mmc_start (struct mmc *mmc)
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{
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qca_mmc *host = mmc->priv;
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writel(readl(host->base + MMCIPOWER) | MCI_SW_RST,
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host->base + MMCIPOWER);
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qca_reg_wr_delay(host);
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while (readl(host->base + MMCIPOWER) & MCI_SW_RST) {
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udelay(10);
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}
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return 0;
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}
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int qca_mmc_init(bd_t *bis, qca_mmc *host)
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{
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struct mmc *mmc;
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mmc = malloc(sizeof(struct mmc));
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if (!mmc) {
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return -ENOMEM;
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}
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memset(mmc, 0, sizeof(struct mmc));
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sprintf(mmc->name, "qca_mmc");
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mmc->priv = host;
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mmc->send_cmd = qca_mmc_send_cmd;
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mmc->set_ios = qca_set_ios;
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mmc->init = qca_mmc_start;
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mmc->getcd = NULL;
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mmc->f_min = 400000;
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mmc->f_max = 52000000;
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mmc->b_max = 512;
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/* voltage either 2.7-3.6V or 1.70 -1.95V */
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mmc->voltages = 0x40FF8080;
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mmc->host_caps = MMC_MODE_8BIT;
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mmc->host_caps |= MMC_MODE_HC;
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mmc_register(mmc);
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host->mmc = mmc;
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host->dev_num = mmc->block_dev.dev;
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return 0;
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}
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118
drivers/mmc/qca_mmc.h
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118
drivers/mmc/qca_mmc.h
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/*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef ___QCA_MMC_H_
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#define ___QCA_MMC_H_
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#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_SW_RST (1 << 7)
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#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_FLOWENA (1 << 12)
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#define MCI_CLK_SELECTIN (1 << 15)
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#define MCI_CLK_WIDEBUS_1 (0 << 10)
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#define MCI_CLK_WIDEBUS_4 (2 << 10)
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#define MCI_CLK_WIDEBUS_8 (3 << 10)
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#define MMCIARGUMENT 0x008
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_ENABLE (1 << 10)
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#define MCI_CPSM_PROGENA (1 << 11)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_RX_DATA_PEND (1 << 20)
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#define MMCIDATACNT 0x030
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#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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#define MCI_SDIOINTRCLR (1 << 22)
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#define MCI_PROGDONECLR (1 << 23)
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#define MCI_ATACMDCOMPLCLR (1 << 24)
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#define MCI_SDIOINTROPECLR (1 << 25)
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#define MCI_CCSTIMEOUTCLR (1 << 26)
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#define MCI_CLEAR_STATIC_MASK \
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(MCI_CMDCRCFAILCLR|MCI_DATACRCFAILCLR|MCI_CMDTIMEOUTCLR|\
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MCI_DATATIMEOUTCLR|MCI_TXUNDERRUNCLR|MCI_RXOVERRUNCLR| \
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MCI_CMDRESPENDCLR|MCI_CMDSENTCLR|MCI_DATAENDCLR| \
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MCI_STARTBITERRCLR|MCI_DATABLOCKENDCLR|MCI_SDIOINTRCLR| \
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MCI_SDIOINTROPECLR|MCI_PROGDONECLR|MCI_ATACMDCOMPLCLR| \
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MCI_CCSTIMEOUTCLR)
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#define MCI_STATUS2 0x06C
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#define MCI_MCLK_REG_WR_ACTIVE (1 << 0)
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#define MMCIFIFO 0x080 /* to 0x0bc */
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/*
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* The size of the FIFO in bytes.
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*/
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#define MCI_FIFOSIZE (16*4)
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#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
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#define MCI_FIFODEPTH 16
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#define MCI_HFIFO_COUNT (MCI_FIFODEPTH / 2)
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#endif /* __QCA_MMC_H_ */
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