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qca-swiss-army-knife: Add support to dump AR9003 chips EEPROM

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Add support to dump base and modal eeprom header of AR9003 family
chips.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
This commit is contained in:
Rajkumar Manoharan 2012-12-04 14:43:38 +05:30 • committed by Luis R. Rodriguez
parent 5fbd4b3d4d
commit 4f5fcc81e5
6 changed files with 3742 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
tools/edump/src/Makefile.am
View file

@ -1,4 +1,4 @@
bin_PROGRAMS = edump
edump_CFLAGS = -Wall $(pciaccess_CFLAGS)
edump_LDADD = $(pciaccess_LIBS)
edump_SOURCES = eep_def.c eep_4k.c eep_9287.c edump.c
edump_SOURCES = eep_def.c eep_4k.c eep_9287.c eep_9003.c edump.c

20
tools/edump/src/edump.c
View file

@ -70,6 +70,13 @@ static struct {
{ AR_SREV_VERSION_9280, "9280" },
{ AR_SREV_VERSION_9285, "9285" },
{ AR_SREV_VERSION_9287, "9287" },
{ AR_SREV_VERSION_9300, "9300" },
{ AR_SREV_VERSION_9330, "9330" },
{ AR_SREV_VERSION_9485, "9485" },
{ AR_SREV_VERSION_9462, "9462" },
{ AR_SREV_VERSION_9565, "9565" },
{ AR_SREV_VERSION_9340, "9340" },
{ AR_SREV_VERSION_9550, "9550" },
};
static const char *
@ -98,7 +105,13 @@ static int is_supported_chipset(struct pci_device *pdev)
(pdev->device_id != AR9280_DEVID_PCIE) &&
(pdev->device_id != AR9285_DEVID_PCIE) &&
(pdev->device_id != AR9287_DEVID_PCI) &&
(pdev->device_id != AR9287_DEVID_PCIE)) {
(pdev->device_id != AR9287_DEVID_PCIE) &&
(pdev->device_id != AR9300_DEVID_PCIE) &&
(pdev->device_id != AR9485_DEVID_PCIE) &&
(pdev->device_id != AR9580_DEVID_PCIE) &&
(pdev->device_id != AR9462_DEVID_PCIE) &&
(pdev->device_id != AR9565_DEVID_PCIE) &&
(pdev->device_id != AR1111_DEVID_PCIE)) {
fprintf(stderr, "Device ID: 0x%x not supported\n", pdev->device_id);
return 0;
}
@ -211,7 +224,10 @@ bool pci_eeprom_read(struct edump *edump, uint32_t off, uint16_t *data)
int register_eep_ops(struct edump *edump)
{
if (AR_SREV_9287(edump)) {
if (AR_SREV_9300_20_OR_LATER(edump)) {
edump->eep_map = EEP_MAP_9003;
edump->eep_ops = &eep_9003_ops;
} else if (AR_SREV_9287(edump)) {
edump->eep_map = EEP_MAP_9287;
edump->eep_ops = &eep_9287_ops;
} else if (AR_SREV_9285(edump)) {

32
tools/edump/src/edump.h
View file

@ -33,6 +33,7 @@
#include "eep_def.h"
#include "eep_4k.h"
#include "eep_9287.h"
#include "eep_9003.h"
#if __BYTE_ORDER == __BIG_ENDIAN
#define REG_READ(_reg) \
@ -61,6 +62,12 @@ typedef int bool;
#define AR9285_DEVID_PCIE 0x002b
#define AR9287_DEVID_PCI 0x002d
#define AR9287_DEVID_PCIE 0x002e
#define AR9300_DEVID_PCIE 0x0030
#define AR9485_DEVID_PCIE 0x0032
#define AR9580_DEVID_PCIE 0x0033
#define AR9462_DEVID_PCIE 0x0034
#define AR9565_DEVID_PCIE 0x0036
#define AR1111_DEVID_PCIE 0x0037
#define AR_SREV 0x4020
#define AR_SREV_ID 0x000000FF
@ -80,6 +87,13 @@ typedef int bool;
#define AR_SREV_VERSION_9280 0x80
#define AR_SREV_VERSION_9285 0xC0
#define AR_SREV_VERSION_9287 0x180
#define AR_SREV_VERSION_9300 0x1c0
#define AR_SREV_VERSION_9330 0x200
#define AR_SREV_VERSION_9485 0x240
#define AR_SREV_VERSION_9462 0x280
#define AR_SREV_VERSION_9565 0x2c0
#define AR_SREV_VERSION_9340 0x300
#define AR_SREV_VERSION_9550 0x400
#define AR_SREV_9280_20_OR_LATER(edump) \
(((edump)->macVersion >= AR_SREV_VERSION_9280))
@ -87,6 +101,20 @@ typedef int bool;
(((edump)->macVersion == AR_SREV_VERSION_9285))
#define AR_SREV_9287(_ah) \
(((edump)->macVersion == AR_SREV_VERSION_9287))
#define AR_SREV_9300_20_OR_LATER(edump) \
(((edump)->macVersion >= AR_SREV_VERSION_9300))
#define AR_SREV_9485(edump) \
(((edump)->macVersion == AR_SREV_VERSION_9485))
#define AR_SREV_9330(edump) \
(((edump)->macVersion == AR_SREV_VERSION_9330))
#define AR_SREV_9340(edump) \
(((edump)->macVersion == AR_SREV_VERSION_9340))
#define AR_SREV_9462(edump) \
(((edump)->macVersion == AR_SREV_VERSION_9462))
#define AR_SREV_9550(edump) \
(((edump)->macVersion == AR_SREV_VERSION_9550))
#define AR_SREV_9565(edump) \
(((edump)->macVersion == AR_SREV_VERSION_9565))
#define AH_WAIT_TIMEOUT 100000 /* (us) */
#define AH_TIME_QUANTUM 10
@ -114,6 +142,7 @@ struct edump {
struct ar5416_eeprom_def def;
struct ar5416_eeprom_4k map4k;
struct ar9287_eeprom map9287;
struct ar9300_eeprom eep_93k;
} eeprom;
};
@ -130,7 +159,10 @@ struct eeprom_ops {
extern struct eeprom_ops eep_def_ops;
extern struct eeprom_ops eep_4k_ops;
extern struct eeprom_ops eep_9287_ops;
extern struct eeprom_ops eep_9003_ops;
bool pci_eeprom_read(struct edump *edump, uint32_t off, uint16_t *data);
bool hw_wait(struct edump *edump, uint32_t reg, uint32_t mask,
uint32_t val, uint32_t timeout);
#endif /* EDUMP_H */

3440
tools/edump/src/eep_9003.c Normal file
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File diff suppressed because it is too large Load diff

247
tools/edump/src/eep_9003.h Normal file
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@ -0,0 +1,247 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef AR9003_EEPROM_H
#define AR9003_EEPROM_H
#include <linux/types.h>
#include <endian.h>
/* 16-bit offset location start of calibration struct */
#define AR9300_NUM_5G_CAL_PIERS 8
#define AR9300_NUM_2G_CAL_PIERS 3
#define AR9300_NUM_5G_20_TARGET_POWERS 8
#define AR9300_NUM_5G_40_TARGET_POWERS 8
#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
#define AR9300_NUM_2G_20_TARGET_POWERS 3
#define AR9300_NUM_2G_40_TARGET_POWERS 3
/* #define AR9300_NUM_CTLS 21 */
#define AR9300_NUM_CTLS_5G 9
#define AR9300_NUM_CTLS_2G 12
#define AR9300_NUM_BAND_EDGES_5G 8
#define AR9300_NUM_BAND_EDGES_2G 4
#define AR9300_CUSTOMER_DATA_SIZE 20
#define AR9300_MAX_CHAINS 3
#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
/* Delta from which to start power to pdadc table */
/* This offset is used in both open loop and closed loop power control
* schemes. In open loop power control, it is not really needed, but for
* the "sake of consistency" it was kept. For certain AP designs, this
* value is overwritten by the value in the flag "pwrTableOffset" just
* before writing the pdadc vs pwr into the chip registers.
*/
#define AR9300_PWR_TABLE_OFFSET 0
/* byte addressable */
#define AR9300_EEPROM_SIZE (16*1024)
#define AR9300_BASE_ADDR_4K 0xfff
#define AR9300_BASE_ADDR 0x3ff
#define AR9300_BASE_ADDR_512 0x1ff
#define AR9300_OTP_BASE 0x14000
#define AR9300_OTP_STATUS 0x15f18
#define AR9300_OTP_STATUS_TYPE 0x7
#define AR9300_OTP_STATUS_VALID 0x4
#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
#define AR9300_OTP_STATUS_SM_BUSY 0x1
#define AR9300_OTP_READ_DATA 0x15f1c
struct eepFlags {
uint8_t opFlags;
uint8_t eepMisc;
} __attribute__ ((packed));
enum CompressAlgorithm {
_CompressNone = 0,
_CompressLzma,
_CompressPairs,
_CompressBlock,
_Compress4,
_Compress5,
_Compress6,
_Compress7,
};
struct ar9300_base_eep_hdr {
int16_t regDmn[2];
/* 4 bits tx and 4 bits rx */
uint8_t txrxMask;
struct eepFlags opCapFlags;
uint8_t rfSilent;
uint8_t blueToothOptions;
uint8_t deviceCap;
/* takes lower byte in eeprom location */
uint8_t deviceType;
/* offset in dB to be added to beginning
* of pdadc table in calibration
*/
int8_t pwrTableOffset;
uint8_t params_for_tuning_caps[2];
/*
* bit0 - enable tx temp comp
* bit1 - enable tx volt comp
* bit2 - enable fastClock - default to 1
* bit3 - enable doubling - default to 1
* bit4 - enable internal regulator - default to 1
*/
uint8_t featureEnable;
/* misc flags: bit0 - turn down drivestrength */
uint8_t miscConfiguration;
uint8_t eepromWriteEnableGpio;
uint8_t wlanDisableGpio;
uint8_t wlanLedGpio;
uint8_t rxBandSelectGpio;
uint8_t txrxgain;
/* SW controlled internal regulator fields */
int32_t swreg;
} __attribute__ ((packed));
struct ar9300_modal_eep_header {
/* 4 idle, t1, t2, b (4 bits per setting) */
int32_t antCtrlCommon;
/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
int32_t antCtrlCommon2;
/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
int16_t antCtrlChain[AR9300_MAX_CHAINS];
/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
uint8_t xatten1DB[AR9300_MAX_CHAINS];
/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
uint8_t xatten1Margin[AR9300_MAX_CHAINS];
int8_t tempSlope;
int8_t voltSlope;
/* spur channels in usual fbin coding format */
uint8_t spurChans[AR_EEPROM_MODAL_SPURS];
/* 3 Check if the register is per chain */
int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
uint8_t reserved[11];
int8_t quick_drop;
uint8_t xpaBiasLvl;
uint8_t txFrameToDataStart;
uint8_t txFrameToPaOn;
uint8_t txClip;
int8_t antennaGain;
uint8_t switchSettling;
int8_t adcDesiredSize;
uint8_t txEndToXpaOff;
uint8_t txEndToRxOn;
uint8_t txFrameToXpaOn;
uint8_t thresh62;
int32_t papdRateMaskHt20;
int32_t papdRateMaskHt40;
int16_t switchcomspdt;
uint8_t xlna_bias_strength;
uint8_t futureModal[7];
} __attribute__ ((packed));
struct ar9300_cal_data_per_freq_op_loop {
int8_t refPower;
/* pdadc voltage at power measurement */
uint8_t voltMeas;
/* pcdac used for power measurement */
uint8_t tempMeas;
/* range is -60 to -127 create a mapping equation 1db resolution */
int8_t rxNoisefloorCal;
/*range is same as noisefloor */
int8_t rxNoisefloorPower;
/* temp measured when noisefloor cal was performed */
uint8_t rxTempMeas;
} __attribute__ ((packed));
struct cal_tgt_pow_legacy {
uint8_t tPow2x[4];
} __attribute__ ((packed));
struct cal_tgt_pow_ht {
uint8_t tPow2x[14];
} __attribute__ ((packed));
struct cal_ctl_data_2g {
uint8_t ctlEdges[AR9300_NUM_BAND_EDGES_2G];
} __attribute__ ((packed));
struct cal_ctl_data_5g {
uint8_t ctlEdges[AR9300_NUM_BAND_EDGES_5G];
} __attribute__ ((packed));
struct ar9300_BaseExtension_1 {
uint8_t ant_div_control;
uint8_t future[3];
uint8_t tempslopextension[8];
int8_t quick_drop_low;
int8_t quick_drop_high;
} __attribute__ ((packed));
struct ar9300_BaseExtension_2 {
int8_t tempSlopeLow;
int8_t tempSlopeHigh;
uint8_t xatten1DBLow[AR9300_MAX_CHAINS];
uint8_t xatten1MarginLow[AR9300_MAX_CHAINS];
uint8_t xatten1DBHigh[AR9300_MAX_CHAINS];
uint8_t xatten1MarginHigh[AR9300_MAX_CHAINS];
} __attribute__ ((packed));
struct ar9300_eeprom {
uint8_t eepromVersion;
uint8_t templateVersion;
uint8_t macAddr[6];
uint8_t custData[AR9300_CUSTOMER_DATA_SIZE];
struct ar9300_base_eep_hdr baseEepHeader;
struct ar9300_modal_eep_header modalHeader2G;
struct ar9300_BaseExtension_1 base_ext1;
uint8_t calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
struct ar9300_cal_data_per_freq_op_loop
calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
uint8_t calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
uint8_t calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
uint8_t calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
uint8_t calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
struct cal_tgt_pow_legacy
calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
struct cal_tgt_pow_legacy
calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
struct cal_tgt_pow_ht
calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
struct cal_tgt_pow_ht
calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
uint8_t ctlIndex_2G[AR9300_NUM_CTLS_2G];
uint8_t ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
struct ar9300_modal_eep_header modalHeader5G;
struct ar9300_BaseExtension_2 base_ext2;
uint8_t calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
struct ar9300_cal_data_per_freq_op_loop
calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
uint8_t calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
uint8_t calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
uint8_t calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
struct cal_tgt_pow_legacy
calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
struct cal_tgt_pow_ht
calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
struct cal_tgt_pow_ht
calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
uint8_t ctlIndex_5G[AR9300_NUM_CTLS_5G];
uint8_t ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
} __attribute__ ((packed));
#endif

5
tools/edump/src/eep_common.h
View file

@ -30,7 +30,9 @@
#define AR5416_EEPROM_S 2
#define AR5416_EEPROM_OFFSET 0x2000
#define AR_EEPROM_STATUS_DATA 0x407c
#define AR_EEPROM_STATUS_DATA (AR_SREV_9340(edump) ? 0x40c8 : \
(AR_SREV_9300_20_OR_LATER(edump) ? \
0x4084 : 0x407c))
#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
#define AR_EEPROM_STATUS_DATA_VAL_S 0
#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
@ -66,6 +68,7 @@ enum eep_map {
EEP_MAP_DEFAULT = 0x0,
EEP_MAP_4K,
EEP_MAP_9287,
EEP_MAP_9003,
EEP_MAP_MAX
};