Steve Markgraf
a187e84865
add external_dualchan_adc for AD9238 boards
2025-11-15 21:21:37 +01:00
Steve Markgraf
1a9131277a
add 8 bit mode for SDR example
2025-06-01 00:32:34 +02:00
montoyatim01
eba89b3877
Dual ADC HDMI Drive & PCM1802 Swap
...
- Fixed the GPIO drive settings for the HDMI output to match the other apps
- Swap the PCM1802 devices to match the order on the Sev5000 PCB
2025-04-22 19:35:43 +02:00
Steve Markgraf
0a948ce64c
switch PCM1802 clock to 40 MHz
...
This avoids picking up the audio clock
with the RF ADC as spurs in the spectrum,
and requires a different PCM1802 mode config
than before for 512fs oversampling:
MODE0 = 1
MODE1 = 0
The resulting audio samplerate is 78125 Hz.
2025-03-23 23:15:37 +01:00
Steve Markgraf
91dff299b5
lib: do not overclock flash chip
...
Some of the chinese RP2350B boards seem to have issues
when overclocking the QSPI flash too much, so keep
the clock within limits.
2025-03-21 01:12:21 +01:00
Steve Markgraf
94096b7489
add support for hsdaohSDR
2025-03-02 21:23:03 +01:00
Steve Markgraf
e293c0c075
decrease ringbuffer for audio
2025-03-02 00:33:18 +01:00
Steve Markgraf
95a7b73bda
add format ID, dual audio support
2025-02-27 23:10:15 +01:00
Steve Markgraf
058c13d4a7
simplify ADC PIO code
2025-02-14 21:26:59 +01:00
Steve Markgraf
c5cf8c1178
make rbuf len configurable, signal overflow to host
2025-02-12 23:22:59 +01:00
Steve Markgraf
1bdf43ae94
lib: make drivestrength and slewrate configurable
2025-02-12 00:16:43 +01:00
Steve Markgraf
6108b0007c
dual_external_adc: correct PIO program name
2025-02-09 00:30:01 +01:00
Steve Markgraf
4b96c498ae
add support for multiple streams, PCM1802 and dual ADC example
2025-02-05 23:15:57 +01:00
Steve Markgraf
32f23da176
ext_adc: fix pin init
2025-01-05 23:33:18 +01:00
Steve Markgraf
fd74049bf4
ext_adc: switch to sys_clk/1 for HSTX
...
For the 40 MHz example we are now running
with a very moderate, almost-in-spec 160 MHz
and no overvolting.
2025-01-05 22:49:28 +01:00
Steve Markgraf
708ead241c
fix initial ringbuffer head value
...
As the first two DMA transfers have already been
submitted during init, the correct start value
is 2.
2025-01-05 01:11:47 +01:00
Steve Markgraf
bae93b3a87
improve performance by using three DMA channels
...
Previously when using an HSTX clock > sysclk/2,
there was a DMA underrun from time to time,
which limited the achievable data rate to
around 75 MByte/s. By using a third DMA channel
and employing some trickery to be still able to
use the DMA CRC sniffer, we now can achieve
128 MByte/s (or even more) by using sysclk/1
as HSTX clock.
The counter example has been updated to
generate those ~128 MByte/s.
2024-12-26 23:18:41 +01:00
Steve Markgraf
560ce9a6a1
add 16 bit logic analyzer example
2024-12-13 00:37:17 +01:00
Steve Markgraf
371c59fc28
external_adc: Switch to GP20 for ADC clock
...
..so that more consecutive pins are available for
attaching an additional audio ADC module.
2024-11-28 21:11:01 +01:00
Steve Markgraf
2e644a593b
initial commit
2024-11-18 00:06:59 +01:00
