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Steve Markgraf fd74049bf4 ext_adc: switch to sys_clk/1 for HSTX 
For the 40 MHz example we are now running
with a very moderate, almost-in-spec 160 MHz
and no overvolting.
2025-01-05 22:49:28 +01:00
..
counter fix initial ringbuffer head value 2025-01-05 01:11:47 +01:00
external_adc ext_adc: switch to sys_clk/1 for HSTX 2025-01-05 22:49:28 +01:00
internal_adc fix initial ringbuffer head value 2025-01-05 01:11:47 +01:00
logic_analyzer fix initial ringbuffer head value 2025-01-05 01:11:47 +01:00
CMakeLists.txt add 16 bit logic analyzer example 2024-12-13 00:37:17 +01:00