ext_adc: switch to sys_clk/1 for HSTX

For the 40 MHz example we are now running
with a very moderate, almost-in-spec 160 MHz
and no overvolting.

README.md

@@ -44,7 +44,7 @@ The data from the internal ADC is streamed out via USB. Default configuration is
 ### external_adc
 
 This app contains a PIO program that reads the data from a 12-bit ADC connected to GP0-GP11, outputs the ADC clock on GP20, and packs the 12 bit samples to 16-bit words to achieve maximum throughput.
-It is meant to be used with cheap AD9226 ADC boards. The default setting is overclocking the RP2350 to 320 MHz and driving the ADC with a 40 MHz clock. With higher overclocking up to 50.25 MHz ADC clock can be used.
+It is meant to be used with cheap AD9226 ADC boards. The default setting is overclocking the RP2350 to 160 MHz and driving the ADC with a 40 MHz clock. With higher overclocking up to 96 MHz ADC clock can be used.
 
 This can be used for sampling the IF of a tuner/downcoverter, as a direct-sampling HF SDR, or for capturing a video signal e.g. with [vhsdecode](https://github.com/oyvindln/vhs-decode).
 For the vhsdecode use-case, there is also an [adapter PCB](https://github.com/Sev5000/Pico2_12bitADC_PCMAudio).

apps/external_adc/adc_12bit_input.pio

@@ -22,8 +22,7 @@ public entry_point:
 	;----------------------------------------------------------------------------------------
 	in pins, 12     side 1		; 12 bits of first sample in ISR					SAMP
 	nop             side 1
-	nop             side 0
-	nop             side 0
+	nop[1]          side 0
 	; ISR is now:   0 0 0 0 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
 	;----------------------------------------------------------------------------------------
 	mov osr, pins   side 1		; 12 bits of second sample in OSR					SAMP
@@ -101,7 +100,7 @@ static inline void adc_12bit_input_program_init(PIO pio, uint sm, uint offset, u
 	// We only receive, so disable the TX FIFO to make the RX FIFO deeper.
 	sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
 
-	sm_config_set_clkdiv(&c, 2.f);
+	sm_config_set_clkdiv(&c, 1.f);
 
 	// Load our configuration, and start the program from the beginning
 	pio_sm_init(pio, sm, offset, &c);

apps/external_adc/external_adc.c

@@ -43,11 +43,12 @@
 #include "picohsdaoh.h"
 #include "adc_12bit_input.pio.h"
 
-/* The PIO is running with sys_clk/2, and needs 4 cycles per sample,
- * so the ADC clock is sys_clk/8 */
-#define SYS_CLK		320000	// 40 MHz ADC clock
-//#define SYS_CLK	384000	// 48 MHz ADC clock
-//#define SYS_CLK	402000	// 50.25 MHz ADC clock, maximum that works on my Pico2 (with overvolting)
+/* The PIO is running with sys_clk/1, and needs 4 cycles per sample,
+ * so the ADC clock is sys_clk/4 */
+#define SYS_CLK		160000	// 40 MHz ADC clock
+//#define SYS_CLK	192000	// 48 MHz ADC clock
+//#define SYS_CLK	320000	// 80 MHz ADC clock
+//#define SYS_CLK	384000	// 96 MHz ADC clock, maximum that works on my Pico2 (with overvolting)
 
 // ADC is attached to GP0 - GP11 with clock on GP20
 #define PIO_INPUT_PIN_BASE 0
@@ -124,16 +125,18 @@ void init_pio_input(void)
 
 int main()
 {
+#ifdef OVERVOLT
 	/* set maximum 'allowed' voltage without voiding warranty */
 	vreg_set_voltage(VREG_VOLTAGE_MAX);
 	sleep_ms(1);
+#endif
 
 	set_sys_clock_khz(SYS_CLK, true);
 
-	/* set HSTX clock to sysclk/2 */
+	/* set HSTX clock to sysclk/1 */
 	hw_write_masked(
 		&clocks_hw->clk[clk_hstx].div,
-		2 << CLOCKS_CLK_HSTX_DIV_INT_LSB,
+		1 << CLOCKS_CLK_HSTX_DIV_INT_LSB,
 		CLOCKS_CLK_HSTX_DIV_INT_BITS
 	);
 

libpicohsdaoh/picohsdaoh.c

@@ -256,6 +256,7 @@ void __scratch_x("") hstx_dma_irq_handler()
 
 		/* on the second last word of the line, insert the CRC16 of the entire line before the last line */
 		next_line[RBUF_SLICE_LEN - 2] = saved_crc;
+		next_line[RBUF_SLICE_LEN - 3] = 0;
 
 		dma_sniff_pipelined_ch = ch_num;