Steve Markgraf bae93b3a87 improve performance by using three DMA channels ... Previously when using an HSTX clock > sysclk/2, there was a DMA underrun from time to time, which limited the achievable data rate to around 75 MByte/s. By using a third DMA channel and employing some trickery to be still able to use the DMA CRC sniffer, we now can achieve 128 MByte/s (or even more) by using sysclk/1 as HSTX clock. The counter example has been updated to generate those ~128 MByte/s.		2024-12-26 23:18:41 +01:00
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counter	improve performance by using three DMA channels	2024-12-26 23:18:41 +01:00
external_adc	external_adc: Switch to GP20 for ADC clock	2024-11-28 21:11:01 +01:00
internal_adc	initial commit	2024-11-18 00:06:59 +01:00
logic_analyzer	add 16 bit logic analyzer example	2024-12-13 00:37:17 +01:00
CMakeLists.txt	add 16 bit logic analyzer example	2024-12-13 00:37:17 +01:00