The MX35UF2GE4AD nand part has support for 8-bit ECC,
2Gb flash density and 128 bytes of OOB. Updating the
correct info in the nand id table.
Change-Id: I21f1bd0a897b92694040dc5908580c80a4b003da
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
The MX35UF4GE4AD-Z4I part has 256 bytes of spare
size. Updating the correct info in the nand table.
Change-Id: Ic3c71d870db8f7e54d0aeb0de27e1812f0fdff7d
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
This change will add support for giga device
GD5F2GM7REYIG spi nand support.
Change-Id: I97772e0a8210bd5a6d41e10bbfbdd75b44e53108
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds the winbond W25N512GW and W25N02KWZEIR devices
and fixes the W25N01GWZEIG device id from 0xBA to 0xBA21,
W25N02JWZEIF device id from 0xBF to 0xBF22 and
W25N01JW device id from 0xBC to 0xBC21
Change-Id: Ic91800386446263477af06c6d39d9051a2dde3b9
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
It has the capacity of 1Gbit, i.e., 128MB, so
the number of blocks has been updated to 1024.
1Gbits = 128MB = 2048(page) * 64 (pages per block) * 1024 (blocks)
Change-Id: I552776e4e151d16782db915c3ebae874c5c02696
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
This change will add support for giga device GD5F1GM7REYIG
spi nand support.
Change-Id: Ie32cb6824bd0fbcf04449fa070005b7fa323c025
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This change fixup the magic word (0xBAD0FF5E) instead of zero.
So the uboot will skip setting qcom,training_offset
if the serial training partition is not present in flash.
Change-Id: I0ee8c9475e1153fdbc295691ceb2a4b1d6fdd394
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
Flash Status register value will get updated in [15:8]
bits section. Hence right shift first and then extract
the required bit value.
Change-Id: I7f2233f22984da3db2324e9e2ba8aafff76adb32
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
Winbond SPI Nand devices provides two different modes for read operations,
Buffer Read Mode (BUF=1) and Continuous Read Mode (BUF=0).
We can configure the BUF bit to read and operate in any one mode.
Change-Id: Ie7adce70642756725e52dab8821333c42fdb601f
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
This change will add support for Winbond "W25N01GWZEIG" spi nand
Change-Id: Ic42938142115408406a8790e114d2d2acfc0dbb5
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
This change will add support for Macronix "MX35UF2GE4AD-Z4I" spi nand
Change-Id: I5d783473c0ec918b02e59a85b71ee941fe649365
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
qpic_nand sbl -> to switch to 2K layout
qpic_nand linux -> to switch back to 4K layout
Currently this switch is enabled for IPQ9574
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
(cherry picked from commit c9a1c10b2e35ba8f14dafc1f4c07aa5a07a01541)
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Change-Id: I3e429b8cd5e600b4214c01d7949c01536f988e47
This change will add support for 4K Macronix spi nand
"MX35UF4GE4AD-Z4I"
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I94e07d9e25de46c67fcb679ef149990e093afc8f
This change will add support for Macronix "MX35UF1GE4AC" spi nand
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I66e82e22217d655b44e30baa64f3aefd5a5f2aaa
This change will add support for winbond "W25N02JWZEIF"
spi nand device.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I1dd258c3f0f3174d09e74fb7ffd0c26a43e6c24b
This change will add support for giga device GD5F1GQ5REYIG
spi nand support.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I57211ce34543de81216d86653a45519b97cf2fb0
This change will change serial training data read to one complete
page instead of 64-bytes read. Partial page read will cause some
data curroption issue if read request failed so read one complete page.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibad101f096440e5dc10dfb4b3329a0aa6bddee7d
This change will fix proper clock source macro in set_clk_rate function.
Currently we are passing the wrong value to qpic_set_clk_rate for clock
source.
wrong:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, NAND_QSPI_MSTR_CONFIG);
The last argument should be clock source not register base address.
correct:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, GPLL0_CLK_SRC);
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ie9e07c253220924fd0c9287f7f0e2c5d42351128
This change will fix memory leak problem in serial training.
For serial tarining we are allocating memory to hold the training
pattern buf. For any failure we are freeing the buffer but due to
wrong lavel used memory was not getting freed due to this memory leak
problem is happening.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I35ffd27df9b24ea53aed9e9f0623d8890ba66f06
This change fix Access violation created by APPS
master by accessing QPIC_XPU issue due to accessing
QPIC_QSPI_MSTR_CONFIG & QPIC_NAND_FLASH_SPI_CFG registers
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ibb840db12359eea01823dd7732fcb1ac1e7b8967
This change will fix erase address configuration for QSPI
nand devices whose density is beyond 128MiB.
To erase a block as per datasheet of serial nand device
page row address <5:0> and the Block row address <16:6>.
In code we are forming directly pages address starting
from <16:0> i.e 17-bit address. Currently we are configuring
address_0 and address_1 register as follws.
addr0 = (page << 16) and addr1 = 0x0;
This logic will work if device size upto 128MiB, but if device
size beyond 128MiB then this logic will fail becasue upper most bit
will go out of add0 register.
Fixing this by changing address configuration logic for erase block.
addr0 = (page << 16) addr1 = (page >> 16) & 0xffff;
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I4950bb611780257629491ffbb42c91fcfedebc58
This change will define qspi_debug macro to print
debug messages.
Change-Id: I49c5278f63fa53dc5b2237aeb9bfef97990ecc86
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will enable config for serial training.
This change also fix the the logic to get most appropriate phase
out of passed phase.
This change also add support to read serial training offset from
partition table. Also patching freqency value & phase value to kernel.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibb4a5cd80f16605e8e91bdf6a0c6c484edff1735
This change will fix NULL pointer dereference while reading
from spi nand flash in oobbuf.
The multipage read features is only to read with ecc for
raw read/write the the access is page wise due to mtd layer
will request only one page at a time. So don't increment oobbuf
for every page while reading if already bitflips are present in spi
nand flash. if so data abort will happen due to NULL pointer
dereference.
error:
NAND read: device 0 offset 0x4480000, size 0x1000
data abort
pc : [<4a9515ec>] lr : [<44000e18>]
reloc pc : [<4a9515ec>] lr : [<44000e18>]
sp : 4a77f6f4 ip : bbfff3dc fp : 4a783510
r10: 4a97bb40 r9 : 4a77feb0 r8 : 44000e0c
r7 : 4a97ca2c r6 : 0000000f r5 : 00000004 r4 : 00000003
r3 : ffffffff r2 : 000001f4 r1 : 000000ff r0 : 44000e0c
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I435f65183b56ceef64bad7d0df7ffebe02175a66
This change will fix serial training logic and enable
config to enable default qpic_io_macro clock @ 80MHz with
default phase delay valu 4 for all qspi serial line.
This change also fix the delay issue while writing to qpic
register via bam.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I345f736fdae9d48b6da0115ca7a8519b43fe9efd
This change will add support to write some ops group register via
BAM to avoid xPU error.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I65ea875f783b7254f01cb3cf43eb43295caa4ed9
This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
