This patch updates the following ethernet configuration
on ipq9574.
Previously, AL06 has qca8075 PHY attached in the UNIPHY0,
now it has been replaced with qca808x PHY mode.
Change-Id: Ieb5b9ef10bd1ebfd1992cbfa10cb02b2ac4d0534
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
RDP467 is same as AL02-C4 with PCIE0 enabled with
wkk support.
Change-Id: If6ba645b7c62a3320139a7c86e0b89ec525a0fb7
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
We want to extract rootfs image from ubi without any
changes, as we are traversing through the rootfs image
for 0xdeadc0de in extract_rootfs_binary() to extract
the image till 0xdeadc0de offset.
Change-Id: Iefeec6db72b65310310d74835b68ec3d22144608
Signed-off-by: Vijay Balaji <quic_vijbal@quicinc.com>
This changes fixup "qcom,controlled-remotely" property and
"qti,config-pipe-trust-reg" property in the crypto bam node
in ATF boot. This will enable the kernel to do complete bam
pipe initialization.
Change-Id: I454c4e4e68354506dc16b1e72b514264778314e0
Signed-off-by: Karthick Shanmugham <quic_kartshan@quicinc.com>
This change adds support to extract rootfs binary
till correct data-block offset and replaces the
binary for image authentication in both
EMMC and Nand flashtypes.
Change-Id: Ib56228a620ffc5bcfae8b51682377b68e273484f
Signed-off-by: Vijay Balaji <quic_vijbal@quicinc.com>
This patch add supports to boot linux 6.1 images on
IPQ5332 & IPQ9574 DB boards.
Change-Id: Ifd9fb1b74c248ffc625c7c49fc96dd7d16a8670f
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This patch adds the XCFG configuration for improving the
performance in the USB compliance test
Adjust HSTX slew rate from 565 ps to 400 ps
Adjust Manual control ODT value from 45.02 Ohm to 33.97 ohm
Adjust HSTX Current of current-mode driver, 17.1mA * 22.5ohm = 385mV
Change-Id: I21a6fc9ff520c36d5cbc4d727e48309d556c8165
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The previous fixup patch will not actually fdt fixup all the
mentioned config name, it will pick the first one only. So
that, 6.1 kernel will not boot up.
So, updating the config name fixup logic for the multiple
config names.
Change-Id: I4197c04c1edcd72e0982ccbf6884617c998880de
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Update SDX reset GPIO to restart SDX during different SSR scenarios.
Change-Id: I8ecda7f08bbb00498736925efb6bc0f834da48a8
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
Changing the data type of phy_chip_id1 and phy_chip_id2 from
32-bit to 16-bit and initializing them to 0 to avoid any junk
value while shifting and concatenating them to form the final
phy_chip_id.
Change-Id: If96b01db9ec2b3c0a259ea3c98516d1f18a898ce
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
We observed that ubi_rootfs volume id is different for ipq807x
and ipq95xx, so we use volume name instead of volume id for
rootfs extraction from ubi.
Change-Id: I0b536fbceae47279b81d76f8108ca8640c09657c
Signed-off-by: Vijay Balaji <quic_vijbal@quicinc.com>
This patch appends the rdp474 name of ap-mi01.9 in config
Change-Id: If97ced31402d4f7bb84fb27f7eb4d53e4f4edfd7
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds the NAND 64M flash support and adds
the new param --flash_size to denote the flash size
Change-Id: I101cf75d2f1d177475052b8f90cb0cdf30731a20
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Reuse DB-MI02.1 for 256M DDR and single QCN64xx radio configuration
Change-Id: Ia08a7705e5254b59cb8f15f5bcba41497fc3eb94
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Variable _load_end_ points to end address of uncompressed buffer
(*not* uncomress_buffer_end / sizeof(ulong)), so multipling uncompressed
size with sizeof(ulong) is grossly incorrect in flush_cache().
It might lead to access of address beyond valid memory range and hang the CPU.
Tested on MIPS architecture by using compressed(gzip, lzma)
and uncompressed uImage.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
Change-Id: Ia93bfc549e348e655a748a24f59b38a0f80659ce
(cherry picked from commit 8d4f11c203)
This RDP is based on AL02-C4, with changes in ethernet for GPON enablement
Change-Id: Ic25d9009e685d8646564bda582305fbf1bce2be6
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This change will add support for rootfs Authentication in all
flashtypes (Nor, Nand, Emmc and norplusnand) during sysupgrade.
Here we are adding support to sign rootfs image with sha384.
The rootfs metadata is available at the end of kernel image.
This change adds supports to extract rootfs metadata from
kernel image and stores in /tmp/metadata.bin.
It also calculates sha384 of rootfs binary and stores in /tmp/sha384_keyXXXXXX
After this we use below command to authenticate rootfs metadata:
echo -n "0x17 /tmp/metadata.bin /tmp/sha384_keyXXXXXX" > /sys/sec_upgrade/sec_auth
Change-Id: Iaf304d5edcd3bfff849fcb3705f5342f4c354b5b
Signed-off-by: Vijay Balaji <quic_vijbal@quicinc.com>
Add support to read the TME-l OEM fuse parameters from
qfprom address
Change-Id: Ia4f0766a68b67fccc59a09883dd7ef11bc970eef
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
if board has emmc flash type,
Ehable EMMC and disable NAND flash in
kernel device tree during kernel bootup
Change-Id: Ibbe197c39c4c4e47d97c33fa9a48d068e85917ab
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
The AP-MI01.9 is similar to AP-MI01.2 with internal
radio disabled and pcie0 for WKK 5G and pcie1 for WKK 2G
Change-Id: I568c4da0c7604881395dad08be42201fdf9c746b
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie0 and usb uses combo phy, for usb 3.0 GCC_PCIE3X1_PHY_AHB_CBCR
clock has to be enabled
Change-Id: I281773f40bf7d32b27a27e7dc5e5d531ae3a3dc0
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch increases the CDR bandwidth to pass the
USB 3.0 Rx jitter tolerance test
Change-Id: Id58b71f4078ea5d60ab0b0d7bf93aa0a5d519e3c
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
