Variable _load_end_ points to end address of uncompressed buffer
(*not* uncomress_buffer_end / sizeof(ulong)), so multipling uncompressed
size with sizeof(ulong) is grossly incorrect in flush_cache().
It might lead to access of address beyond valid memory range and hang the CPU.
Tested on MIPS architecture by using compressed(gzip, lzma)
and uncompressed uImage.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
Change-Id: Ia93bfc549e348e655a748a24f59b38a0f80659ce
(cherry picked from commit 8d4f11c203)
This RDP is based on AL02-C4, with changes in ethernet for GPON enablement
Change-Id: Ic25d9009e685d8646564bda582305fbf1bce2be6
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This change will add support for rootfs Authentication in all
flashtypes (Nor, Nand, Emmc and norplusnand) during sysupgrade.
Here we are adding support to sign rootfs image with sha384.
The rootfs metadata is available at the end of kernel image.
This change adds supports to extract rootfs metadata from
kernel image and stores in /tmp/metadata.bin.
It also calculates sha384 of rootfs binary and stores in /tmp/sha384_keyXXXXXX
After this we use below command to authenticate rootfs metadata:
echo -n "0x17 /tmp/metadata.bin /tmp/sha384_keyXXXXXX" > /sys/sec_upgrade/sec_auth
Change-Id: Iaf304d5edcd3bfff849fcb3705f5342f4c354b5b
Signed-off-by: Vijay Balaji <quic_vijbal@quicinc.com>
Add support to read the TME-l OEM fuse parameters from
qfprom address
Change-Id: Ia4f0766a68b67fccc59a09883dd7ef11bc970eef
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
if board has emmc flash type,
Ehable EMMC and disable NAND flash in
kernel device tree during kernel bootup
Change-Id: Ibbe197c39c4c4e47d97c33fa9a48d068e85917ab
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
The AP-MI01.9 is similar to AP-MI01.2 with internal
radio disabled and pcie0 for WKK 5G and pcie1 for WKK 2G
Change-Id: I568c4da0c7604881395dad08be42201fdf9c746b
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie0 and usb uses combo phy, for usb 3.0 GCC_PCIE3X1_PHY_AHB_CBCR
clock has to be enabled
Change-Id: I281773f40bf7d32b27a27e7dc5e5d531ae3a3dc0
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch increases the CDR bandwidth to pass the
USB 3.0 Rx jitter tolerance test
Change-Id: Id58b71f4078ea5d60ab0b0d7bf93aa0a5d519e3c
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This change will add support for giga device
GD5F2GM7REYIG spi nand support.
Change-Id: I97772e0a8210bd5a6d41e10bbfbdd75b44e53108
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
In AP-MI01.3 RDP, PCIe0 and PCIe1 are enabled in single
lane configuration
Change-Id: I5592d50ebb425a92ad536142573d09cdd60206b2
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Adding a new command 'flupdate' to change the flash type
to mmc/nand/nor. flupdate set will set the flash type to
the provided type. flupdate clear will reset the flash
type to default.
Command usage:
flupdate set mmc/nand/nor
flupdate clear
Change-Id: Ib328cc1fea0b37f27e6479d55fce08365fbfcf69
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
If flash image type is emmc, switch the flash
type to emmc from nor in norplusemmc board using
the flupdate commands. Once the image is flashed
switch back the flash type to nor using the same
flupdate commands.
This change is to support the below Change-Id
Ib328cc1fea0b37f27e6479d55fce08365fbfcf69
Change-Id: Ia5f75923d7bdfd313a986826f1ac2f7f571c414a
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
update the port clock setting for qca8084 PHY with respect to
10M speed configuration.
Change-Id: I16403b155f31f37a6bdf828150ca2d0923a29f3e
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This change checks if 0:CDT_1 partition exists and then flashes cdt.bin.
Previously, check existed only for 0:CDT. The change allows for creation
of single image with proper cdt_1 name and appends it to the single image.
With this, we can successfully use the CDT_1 alternate partition for images.
Change-Id: I100dc789b54805c699ba6f30d5cb1b74734b1bd9
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This patch updates the PCIe1 lane configuration for DB-MI01.1
and DB-MI02.1
Change-Id: I3dc15a3255d74fcbd5147b2fa6f89c184e48410b
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch updates the AP-MI04.1 PCIe configuration from
PCIe0 and PCIe1 to PCIe1 and PCIe2
Change-Id: If4aa155cc1005becd050fbc36d91d3764005c4c4
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Previously 100M speed is not working in port 4 of MHT
by-pass mode. SGMII speed fixup required to dynamically
adjust the gcc clock based on the link-speed.
Still, this is requried only for port 4, because remaining
ports (1-3) will be taken care from switch core. So, added
speed fix for the by-mode support.
Change-Id: I495aad4b64de12ae7f57c0bdb9e0def08ad38681
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
This patch adds the ethernet support for AP-MI01.3 and
removes pci nodes from dts
Change-Id: I3fcb338a061d732b44409aa835a1fde45508be95
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
