This change will clear the divider value while doing deinit of
SD devices. In-order to clear the divider value we have to write
into register GCC_SDCC1_MISC.
Writing 0x0 to this register will clear the divider value which is
set, while doing initialization got SD devices.
Without this change, while kernel bootup we can see the below error.
error:
[3.529917] mmc0: Skipping voltage switch
[4.131741] mmc0: error -110 whilst initialising SD card.
Change-Id: Ifeca94ae09532a4b506e645cc9254e438179c886
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
1. Added emmc clk reset during mmc deinitialization to
avoid the mmc init failure in kernal bootup.
2. Clock has been configured to 192 Mhz for SDHCI mode
3. Proper register is used for disabling emmc clock
Change-Id: Id21e294380ee904027e5d6d2b2929acbd7bac672
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
As 52Mhz clk does not have 50% dutycycle, setting
48MHz clk for mmc data transfer mode
Change-Id: Id9c0ce07fe652df7d575c5ea11f1d83eab0fb24c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
As the U-boot source is going to be common between ARM and MIPS
architecture , it is required to pick only the files specific
to the respective architectures during the build.
So, move the qca arm target specific common files to another
sub level by specifying the ARCH arm.
Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
This patch initialize TLV and CPU context dump size,
required for crashdump collection in flash.
Change-Id: I960300c3ea6c97481a7c5fd551b648454c13deef
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
