This changes fixup "qcom,controlled-remotely" property and
"qti,config-pipe-trust-reg" property in the crypto bam node
in ATF boot. This will enable the kernel to do complete bam
pipe initialization.
Change-Id: I454c4e4e68354506dc16b1e72b514264778314e0
Signed-off-by: Karthick Shanmugham <quic_kartshan@quicinc.com>
This patch adds the XCFG configuration for improving the
performance in the USB compliance test
Adjust HSTX slew rate from 565 ps to 400 ps
Adjust Manual control ODT value from 45.02 Ohm to 33.97 ohm
Adjust HSTX Current of current-mode driver, 17.1mA * 22.5ohm = 385mV
Change-Id: I21a6fc9ff520c36d5cbc4d727e48309d556c8165
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The previous fixup patch will not actually fdt fixup all the
mentioned config name, it will pick the first one only. So
that, 6.1 kernel will not boot up.
So, updating the config name fixup logic for the multiple
config names.
Change-Id: I4197c04c1edcd72e0982ccbf6884617c998880de
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Add support to read the TME-l OEM fuse parameters from
qfprom address
Change-Id: Ia4f0766a68b67fccc59a09883dd7ef11bc970eef
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
if board has emmc flash type,
Ehable EMMC and disable NAND flash in
kernel device tree during kernel bootup
Change-Id: Ibbe197c39c4c4e47d97c33fa9a48d068e85917ab
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
The pcie0 and usb uses combo phy, for usb 3.0 GCC_PCIE3X1_PHY_AHB_CBCR
clock has to be enabled
Change-Id: I281773f40bf7d32b27a27e7dc5e5d531ae3a3dc0
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch increases the CDR bandwidth to pass the
USB 3.0 Rx jitter tolerance test
Change-Id: Id58b71f4078ea5d60ab0b0d7bf93aa0a5d519e3c
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds a condition to power cycle the
SDX based on the current status of the e911 call.
Change-Id: Id3cf50cfb49a26151c98b7d52e18b9c487cfb935
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
This patch removes the support for dumpinfo_s structure to have
uniform EBICS0 bin for both sec and non-sec boots as the Read As Zero
(RAZ) flag has been enabled to protect code and data regions of TZ
Change-Id: I0508677f7dbc4040660d7dd122d7a5d79554ce60
Signed-off-by: quic_abilj <quic_abilj@quicinc.com>
This changes skips the re-initiation of ethernet
if boot fails, preventing ethernet from becoming unstable.
Change-Id: If46a54839db9986ed158b36bf9efb81c3412c88e
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This patch adds the XCFG configuration in HS PHY sequence
to reduce the noise in High Speed TX Eye
Change-Id: Iac430aa8bbd9ccc9a84c164578a1b6e35b3771f8
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The CRASHDUMP RESET bit of TCSR_BOOT_MISC_DETECT Register
has to be set in the crashdump collection path before reset
from u-boot for the TZ to differentiate between the
normal reset and crashdump reset from u-boot and
to retain the crash reason.
Change-Id: Ic74cec02bf749925e599ee12205257480a234064
Signed-off-by: Priyanka MA <quic_priyma@quicnic.com>
This patch adds support to power cycle the SDX device during
the IPQ crash scenario by toggling the full_power_on and reset
gpios.
Change-Id: Ifac2db5480c13456ef50b6d779691c5bf41f21b2
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
This change adds an additional condition to check for empty string as
env variable
Change-Id: Ica847b7af6d28094df54677fa7423e606699f5fe
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
With this change, Add option to support
prefixing crash dump files with timestamp prefix
Change-Id: I30343e6d7dc58376264dd34a4a3cd25bb34e65c6
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This change will read calibration data from the 0:ART partition and
apply it to the appropriate registers.
Change-Id: Ic9360c0fce229c1d1867ee897b811abc56d2b1c7
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
When xbl logs are disabled no logs came in uart console
due to gcc_blsp1_ahb_clk in disabled state.
This patch enables gcc_blsp1_ahb_clk in u-boot to avoid this issue.
Change-Id: I161b003096544e54d3d230027c2665e8fa3d0f5e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The main loop contains an eth init sequence,
to achieve this, remove the eth init sequence
from bootipq.avoid reinitialization.
Support for the IPQ5332 SoC has been added.
Change-Id: I18406dc90ba6845ce367215a55794ba5e400d5d3
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This change creates Al02-c9 dts file to help with pci enumeration
Change-Id: I9a743de8ebbdc3f4ee43c14204ab1244e8945a12
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
This patch removes the flash detection code in fdtfixup as it will be
taken care based on the boot flash type
Reference Commit:
425d52cd85 (avoid multiple machid for nand/mmc boot)
Change-Id: I51739ae539a568a1480a26fb9143be01306ce39a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
