From 22819526738651d939f369b33d25b9dbc87c4c79 Mon Sep 17 00:00:00 2001 From: Antony Arun T Date: Wed, 21 Mar 2018 16:32:44 +0530 Subject: [PATCH 1/2] mmc: waiting for the card to exit from busy state Since OCR value is changed,1ms delay is added to give cards time to respond. Change-Id: I18bddbc9d01ab2c62529c9f2065331f83b7ecca9 Signed-off-by: Antony Arun T --- drivers/mmc/mmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 0320942aa9..6d401bc17f 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -385,6 +385,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) if (err) return err; mmc->ocr = cmd.response[0]; + + /*1ms delay is added to give cards time to respond*/ + if(!use_arg) + udelay(1000); + return 0; } @@ -416,6 +421,7 @@ static int mmc_complete_op_cond(struct mmc *mmc) uint start; int err; + udelay(100); mmc->op_cond_pending = 0; if (!(mmc->ocr & OCR_BUSY)) { start = get_timer(0); From 0ecdac3feaeddb1d0014facb80b627bf21ffce53 Mon Sep 17 00:00:00 2001 From: Antony Arun T Date: Wed, 21 Mar 2018 17:18:47 +0530 Subject: [PATCH 2/2] ipq806x: enabled dcache support Change-Id: Ibfb0cfeb2e6b1919f4debc4d689426ee3ba29702 Signed-off-by: Antony Arun T --- board/qca/arm/common/board_init.c | 4 ++-- board/qca/arm/ipq806x/ipq806x.c | 12 ++++++++++++ include/configs/ipq806x.h | 2 +- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/board/qca/arm/common/board_init.c b/board/qca/arm/common/board_init.c index 19f1bf6a51..ca6fafd452 100644 --- a/board/qca/arm/common/board_init.c +++ b/board/qca/arm/common/board_init.c @@ -343,12 +343,12 @@ void report_l2err(u32 l2esr) } #endif -void enable_caches(void) +__weak void enable_caches(void) { icache_enable(); } -void disable_caches(void) +__weak void disable_caches(void) { icache_disable(); } diff --git a/board/qca/arm/ipq806x/ipq806x.c b/board/qca/arm/ipq806x/ipq806x.c index 57fc729601..b23e609ffa 100644 --- a/board/qca/arm/ipq806x/ipq806x.c +++ b/board/qca/arm/ipq806x/ipq806x.c @@ -968,3 +968,15 @@ void clear_l2cache_err(void) set_l2_indirect_reg(L2ESR_IND_ADDR, val); #endif } + +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + +void disable_caches(void) +{ + icache_disable(); + dcache_disable(); +} diff --git a/include/configs/ipq806x.h b/include/configs/ipq806x.h index 06b2f1e6e4..52129cf025 100644 --- a/include/configs/ipq806x.h +++ b/include/configs/ipq806x.h @@ -334,7 +334,7 @@ typedef struct { * Cache flush and invalidation based on L1 cache, so the cache line * size is configured to 64 */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_DCACHE_OFF +/*#define CONFIG_SYS_DCACHE_OFF*/ /* Enabling this flag will report any L2 errors. * By default we are disabling it */