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MIPS: qca953x: Modify target files to use compile flags directly

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Changes to use the C Flags pushed by the openwrt package directly
from within the qca953x target sources is done.

Change-Id: Ib66cdf88ccef33e7805cc7a6831200502d7f1c23
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
This commit is contained in:
Prabhu Jayakumar 2017-01-09 17:05:45 +05:30
parent 290b4e0b2d
commit 4f520fbf29
7 changed files with 46 additions and 36 deletions
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14
board/qca/mips32/qca953x/board953x.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -23,7 +23,7 @@
extern int ath_ddr_initial_config(uint32_t refresh);
extern int ath_ddr_find_size(void);
#ifdef COMPRESSED_UBOOT
#if COMPRESSED_UBOOT
# define prmsg(...)
# define args char *s
# define board_str(a) do { \
@ -42,9 +42,9 @@ extern int ath_ddr_find_size(void);
# define board_str(a) \
uint32_t revid; \
if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) \
printf(a " - Honey Bee 1.%d", revid & 0xf); \
printf(a " - Honey Bee 1.%d\n", revid & 0xf); \
else \
printf(a " - Honey Bee 2.%d", revid & 0xf);
printf(a " - Honey Bee 2.%d\n", revid & 0xf);
#endif
void
@ -120,9 +120,11 @@ ath_mem_config(void)
tap = (uint32_t *)0xbd001f10;
prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]);
tap = (uint32_t *)TAP_CONTROL_0_ADDRESS;
prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n",
tap[0], tap[2], tap[2], tap[3]);
ath_reg_rd(TAP_CONTROL_0_ADDRESS),
ath_reg_rd(TAP_CONTROL_1_ADDRESS),
ath_reg_rd(TAP_CONTROL_2_ADDRESS),
ath_reg_rd(TAP_CONTROL_3_ADDRESS));
/* Take WMAC out of reset */
reg32 = ath_reg_rd(RST_RESET_ADDRESS);

2
board/qca/mips32/qca953x/extra.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and

2
board/qca/mips32/qca953x/flash.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and

36
board/qca/mips32/qca953x/init-953x.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -165,14 +165,16 @@ ath_ddr_initial_config(uint32_t refresh)
#if !defined(CONFIG_ATH_EMULATION)
int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
mod_val_init, cycle_val, tap_val, type, ctl_config;
uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F;
uint32_t *pll_config = (unsigned *)PLL_CONFIG_VAL_F;
uint32_t bootstrap,revid;
#if !defined(CONFIG_DISPLAY_BOARDINFO)
prmsg("\nsri\n");
if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140)
prmsg("Honey Bee 1.%d\n", revid & 0xf);
else
prmsg("Honey Bee 2.%d\n", revid & 0xf);
#endif
bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS);
@ -336,7 +338,7 @@ ath_uart_freq(void)
void ath_sys_frequency()
{
#if !defined(CONFIG_ATH_EMULATION)
uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl;
uint32_t pll_config, out_div, ref_div, nint, frac, clk_ctrl;
#endif
uint32_t ref = ath_uart_freq();
uint32_t ath_cpu_freq = 0, ath_ddr_freq = 0, ath_ahb_freq = 0;
@ -353,23 +355,23 @@ void ath_sys_frequency()
clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL);
pll = ath_reg_rd(ATH_PLL_CONFIG);
out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll);
ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll);
nint = CPU_PLL_CONFIG_NINT_GET(pll);
frac = CPU_PLL_CONFIG_NFRAC_GET(pll);
pll = ref >> 6;
frac = frac * pll / ref_div;
pll_config = ath_reg_rd(ATH_PLL_CONFIG);
out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll_config);
ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll_config);
nint = CPU_PLL_CONFIG_NINT_GET(pll_config);
frac = CPU_PLL_CONFIG_NFRAC_GET(pll_config);
pll_config = ref >> 6;
frac = frac * pll_config / ref_div;
ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
(CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1);
pll = ath_reg_rd(ATH_DDR_PLL_CONFIG);
out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll);
ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll);
nint = DDR_PLL_CONFIG_NINT_GET(pll);
frac = DDR_PLL_CONFIG_NFRAC_GET(pll);
pll = ref >> 10;
frac = frac * pll / ref_div;
pll_config = ath_reg_rd(ATH_DDR_PLL_CONFIG);
out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll_config);
ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll_config);
nint = DDR_PLL_CONFIG_NINT_GET(pll_config);
frac = DDR_PLL_CONFIG_NFRAC_GET(pll_config);
pll_config = ref >> 10;
frac = frac * pll_config / ref_div;
ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
(CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1);

4
board/qca/mips32/qca953x/qca-eth-953x.h
View file

@ -60,11 +60,11 @@ typedef struct {
#define ath_gmac_reg_rmw_clear(_mac, _x, _y) \
ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y))
#ifdef COMPRESSED_UBOOT
#if COMPRESSED_UBOOT
#define _1000BASET 1000
#define _100BASET 100
#define _10BASET 10
#endif /* #ifdef COMPRESSED_UBOOT */
#endif /* #if COMPRESSED_UBOOT */
/*
* spd is _1000BASET, _100BASET etc. defined in include/miiphy.h

5
include/953x.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -868,8 +868,7 @@
#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
#define TAP_CONTROL_0_ADDRESS 0x1800001c /* Causes exception on u-boot-2016 */
#define TAP_CONTROL_0_ADDRESS 0xB800001c
#define TAP_CONTROL_0_ADDRESS 0x1800001c
#define TAP_CONTROL_1_ADDRESS 0x18000020
#define TAP_CONTROL_2_ADDRESS 0x18000024
#define TAP_CONTROL_3_ADDRESS 0x18000028

11
include/configs/qca953x.h
View file

@ -153,20 +153,27 @@
/*#define CONFIG_USB 1*/
#if pll
#define CFG_PLL_FREQ (pll)
#else
#define CFG_PLL_FREQ CFG_PLL_650_600_200
#endif
#define CONFIG_ATH_SOC 1
#define CONFIG_ATHEROS 1
#define CONFIG_MACH_QCA953x 1
#define CFG_INIT_STACK_IN_SRAM 1
#define CONFIG_AP147 1
#define __CONFIG_BOARD_NAME ap147
#define CONFIG_BOARD_NAME "ap147"
#define BUILD_VERSION "g36c341f-dirty-1"
#define CFG_PLL_FREQ CFG_PLL_650_600_200
#define CFG_ATHRS27_PHY 1
#define CFG_ATH_GMAC_NMACS 2
#define BOARD_NAME "AP147"
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CUSTOM_BOARDINFO 1
#define CONFIG_SYS_TEXT_BASE 0x9f000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000