From 4f520fbf29118c35b61f32cc4f6c1c22de4a03bf Mon Sep 17 00:00:00 2001 From: Prabhu Jayakumar Date: Mon, 9 Jan 2017 17:05:45 +0530 Subject: [PATCH] MIPS: qca953x: Modify target files to use compile flags directly Changes to use the C Flags pushed by the openwrt package directly from within the qca953x target sources is done. Change-Id: Ib66cdf88ccef33e7805cc7a6831200502d7f1c23 Signed-off-by: Prabhu Jayakumar --- board/qca/mips32/qca953x/board953x.c | 14 ++++---- board/qca/mips32/qca953x/extra.c | 2 +- board/qca/mips32/qca953x/flash.c | 2 +- board/qca/mips32/qca953x/init-953x.c | 44 +++++++++++++------------ board/qca/mips32/qca953x/qca-eth-953x.h | 4 +-- include/953x.h | 5 ++- include/configs/qca953x.h | 11 +++++-- 7 files changed, 46 insertions(+), 36 deletions(-) diff --git a/board/qca/mips32/qca953x/board953x.c b/board/qca/mips32/qca953x/board953x.c index 696fe58077..5419ad1f84 100644 --- a/board/qca/mips32/qca953x/board953x.c +++ b/board/qca/mips32/qca953x/board953x.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,7 +23,7 @@ extern int ath_ddr_initial_config(uint32_t refresh); extern int ath_ddr_find_size(void); -#ifdef COMPRESSED_UBOOT +#if COMPRESSED_UBOOT # define prmsg(...) # define args char *s # define board_str(a) do { \ @@ -42,9 +42,9 @@ extern int ath_ddr_find_size(void); # define board_str(a) \ uint32_t revid; \ if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) \ - printf(a " - Honey Bee 1.%d", revid & 0xf); \ + printf(a " - Honey Bee 1.%d\n", revid & 0xf); \ else \ - printf(a " - Honey Bee 2.%d", revid & 0xf); + printf(a " - Honey Bee 2.%d\n", revid & 0xf); #endif void @@ -120,9 +120,11 @@ ath_mem_config(void) tap = (uint32_t *)0xbd001f10; prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]); - tap = (uint32_t *)TAP_CONTROL_0_ADDRESS; prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n", - tap[0], tap[2], tap[2], tap[3]); + ath_reg_rd(TAP_CONTROL_0_ADDRESS), + ath_reg_rd(TAP_CONTROL_1_ADDRESS), + ath_reg_rd(TAP_CONTROL_2_ADDRESS), + ath_reg_rd(TAP_CONTROL_3_ADDRESS)); /* Take WMAC out of reset */ reg32 = ath_reg_rd(RST_RESET_ADDRESS); diff --git a/board/qca/mips32/qca953x/extra.c b/board/qca/mips32/qca953x/extra.c index c5b0ea87a8..6c9b660195 100644 --- a/board/qca/mips32/qca953x/extra.c +++ b/board/qca/mips32/qca953x/extra.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/board/qca/mips32/qca953x/flash.c b/board/qca/mips32/qca953x/flash.c index 9dd9435233..54c785b47a 100644 --- a/board/qca/mips32/qca953x/flash.c +++ b/board/qca/mips32/qca953x/flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/board/qca/mips32/qca953x/init-953x.c b/board/qca/mips32/qca953x/init-953x.c index e0abf20649..dc85d95cf1 100644 --- a/board/qca/mips32/qca953x/init-953x.c +++ b/board/qca/mips32/qca953x/init-953x.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -165,14 +165,16 @@ ath_ddr_initial_config(uint32_t refresh) #if !defined(CONFIG_ATH_EMULATION) int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val, mod_val_init, cycle_val, tap_val, type, ctl_config; - uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F; + uint32_t *pll_config = (unsigned *)PLL_CONFIG_VAL_F; uint32_t bootstrap,revid; +#if !defined(CONFIG_DISPLAY_BOARDINFO) prmsg("\nsri\n"); if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) prmsg("Honey Bee 1.%d\n", revid & 0xf); else prmsg("Honey Bee 2.%d\n", revid & 0xf); +#endif bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS); @@ -336,7 +338,7 @@ ath_uart_freq(void) void ath_sys_frequency() { #if !defined(CONFIG_ATH_EMULATION) - uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl; + uint32_t pll_config, out_div, ref_div, nint, frac, clk_ctrl; #endif uint32_t ref = ath_uart_freq(); uint32_t ath_cpu_freq = 0, ath_ddr_freq = 0, ath_ahb_freq = 0; @@ -353,23 +355,23 @@ void ath_sys_frequency() clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL); - pll = ath_reg_rd(ATH_PLL_CONFIG); - out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll); - ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll); - nint = CPU_PLL_CONFIG_NINT_GET(pll); - frac = CPU_PLL_CONFIG_NFRAC_GET(pll); - pll = ref >> 6; - frac = frac * pll / ref_div; + pll_config = ath_reg_rd(ATH_PLL_CONFIG); + out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll_config); + ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll_config); + nint = CPU_PLL_CONFIG_NINT_GET(pll_config); + frac = CPU_PLL_CONFIG_NFRAC_GET(pll_config); + pll_config = ref >> 6; + frac = frac * pll_config / ref_div; ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) / (CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1); - pll = ath_reg_rd(ATH_DDR_PLL_CONFIG); - out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll); - ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll); - nint = DDR_PLL_CONFIG_NINT_GET(pll); - frac = DDR_PLL_CONFIG_NFRAC_GET(pll); - pll = ref >> 10; - frac = frac * pll / ref_div; + pll_config = ath_reg_rd(ATH_DDR_PLL_CONFIG); + out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll_config); + ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll_config); + nint = DDR_PLL_CONFIG_NINT_GET(pll_config); + frac = DDR_PLL_CONFIG_NFRAC_GET(pll_config); + pll_config = ref >> 10; + frac = frac * pll_config / ref_div; ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) / (CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1); @@ -382,8 +384,8 @@ void ath_sys_frequency() } #endif done: - prmsg("cpu %u ddr %u ahb %u\n", - ath_cpu_freq / 1000000, - ath_ddr_freq / 1000000, - ath_ahb_freq / 1000000); + prmsg("cpu %u ddr %u ahb %u\n", + ath_cpu_freq / 1000000, + ath_ddr_freq / 1000000, + ath_ahb_freq / 1000000); } diff --git a/board/qca/mips32/qca953x/qca-eth-953x.h b/board/qca/mips32/qca953x/qca-eth-953x.h index f1dd260c09..a349c88646 100644 --- a/board/qca/mips32/qca953x/qca-eth-953x.h +++ b/board/qca/mips32/qca953x/qca-eth-953x.h @@ -60,11 +60,11 @@ typedef struct { #define ath_gmac_reg_rmw_clear(_mac, _x, _y) \ ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y)) -#ifdef COMPRESSED_UBOOT +#if COMPRESSED_UBOOT #define _1000BASET 1000 #define _100BASET 100 #define _10BASET 10 -#endif /* #ifdef COMPRESSED_UBOOT */ +#endif /* #if COMPRESSED_UBOOT */ /* * spd is _1000BASET, _100BASET etc. defined in include/miiphy.h diff --git a/include/953x.h b/include/953x.h index 23ede5b7d7..f1b731fef3 100644 --- a/include/953x.h +++ b/include/953x.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -868,8 +868,7 @@ #define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018 -#define TAP_CONTROL_0_ADDRESS 0x1800001c /* Causes exception on u-boot-2016 */ -#define TAP_CONTROL_0_ADDRESS 0xB800001c +#define TAP_CONTROL_0_ADDRESS 0x1800001c #define TAP_CONTROL_1_ADDRESS 0x18000020 #define TAP_CONTROL_2_ADDRESS 0x18000024 #define TAP_CONTROL_3_ADDRESS 0x18000028 diff --git a/include/configs/qca953x.h b/include/configs/qca953x.h index d4edb58975..e9de16a13e 100644 --- a/include/configs/qca953x.h +++ b/include/configs/qca953x.h @@ -153,20 +153,27 @@ /*#define CONFIG_USB 1*/ +#if pll +#define CFG_PLL_FREQ (pll) +#else +#define CFG_PLL_FREQ CFG_PLL_650_600_200 +#endif + #define CONFIG_ATH_SOC 1 #define CONFIG_ATHEROS 1 #define CONFIG_MACH_QCA953x 1 #define CFG_INIT_STACK_IN_SRAM 1 -#define CONFIG_AP147 1 #define __CONFIG_BOARD_NAME ap147 #define CONFIG_BOARD_NAME "ap147" #define BUILD_VERSION "g36c341f-dirty-1" -#define CFG_PLL_FREQ CFG_PLL_650_600_200 #define CFG_ATHRS27_PHY 1 #define CFG_ATH_GMAC_NMACS 2 #define BOARD_NAME "AP147" #define CONFIG_LAST_STAGE_INIT +#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_CUSTOM_BOARDINFO 1 + #define CONFIG_SYS_TEXT_BASE 0x9f000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000