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MIPS: qca953x: Modify target files to use compile flags directly
Changes to use the C Flags pushed by the openwrt package directly from within the qca953x target sources is done. Change-Id: Ib66cdf88ccef33e7805cc7a6831200502d7f1c23 Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
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7 changed files with 46 additions and 36 deletions
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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* Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* it under the terms of the GNU General Public License version 2 and
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@ -23,7 +23,7 @@
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extern int ath_ddr_initial_config(uint32_t refresh);
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extern int ath_ddr_initial_config(uint32_t refresh);
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extern int ath_ddr_find_size(void);
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extern int ath_ddr_find_size(void);
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#ifdef COMPRESSED_UBOOT
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#if COMPRESSED_UBOOT
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# define prmsg(...)
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# define prmsg(...)
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# define args char *s
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# define args char *s
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# define board_str(a) do { \
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# define board_str(a) do { \
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@ -42,9 +42,9 @@ extern int ath_ddr_find_size(void);
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# define board_str(a) \
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# define board_str(a) \
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uint32_t revid; \
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uint32_t revid; \
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if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) \
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if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) \
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printf(a " - Honey Bee 1.%d", revid & 0xf); \
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printf(a " - Honey Bee 1.%d\n", revid & 0xf); \
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else \
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else \
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printf(a " - Honey Bee 2.%d", revid & 0xf);
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printf(a " - Honey Bee 2.%d\n", revid & 0xf);
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#endif
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#endif
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void
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void
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@ -120,9 +120,11 @@ ath_mem_config(void)
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tap = (uint32_t *)0xbd001f10;
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tap = (uint32_t *)0xbd001f10;
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prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]);
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prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]);
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tap = (uint32_t *)TAP_CONTROL_0_ADDRESS;
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prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n",
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prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n",
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tap[0], tap[2], tap[2], tap[3]);
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ath_reg_rd(TAP_CONTROL_0_ADDRESS),
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ath_reg_rd(TAP_CONTROL_1_ADDRESS),
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ath_reg_rd(TAP_CONTROL_2_ADDRESS),
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ath_reg_rd(TAP_CONTROL_3_ADDRESS));
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/* Take WMAC out of reset */
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/* Take WMAC out of reset */
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reg32 = ath_reg_rd(RST_RESET_ADDRESS);
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reg32 = ath_reg_rd(RST_RESET_ADDRESS);
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* it under the terms of the GNU General Public License version 2 and
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* it under the terms of the GNU General Public License version 2 and
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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* Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* it under the terms of the GNU General Public License version 2 and
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@ -165,14 +165,16 @@ ath_ddr_initial_config(uint32_t refresh)
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#if !defined(CONFIG_ATH_EMULATION)
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#if !defined(CONFIG_ATH_EMULATION)
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int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
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int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
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mod_val_init, cycle_val, tap_val, type, ctl_config;
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mod_val_init, cycle_val, tap_val, type, ctl_config;
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uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F;
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uint32_t *pll_config = (unsigned *)PLL_CONFIG_VAL_F;
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uint32_t bootstrap,revid;
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uint32_t bootstrap,revid;
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#if !defined(CONFIG_DISPLAY_BOARDINFO)
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prmsg("\nsri\n");
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prmsg("\nsri\n");
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if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140)
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if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140)
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prmsg("Honey Bee 1.%d\n", revid & 0xf);
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prmsg("Honey Bee 1.%d\n", revid & 0xf);
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else
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else
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prmsg("Honey Bee 2.%d\n", revid & 0xf);
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prmsg("Honey Bee 2.%d\n", revid & 0xf);
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#endif
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bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS);
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bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS);
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@ -336,7 +338,7 @@ ath_uart_freq(void)
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void ath_sys_frequency()
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void ath_sys_frequency()
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{
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{
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#if !defined(CONFIG_ATH_EMULATION)
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#if !defined(CONFIG_ATH_EMULATION)
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uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl;
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uint32_t pll_config, out_div, ref_div, nint, frac, clk_ctrl;
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#endif
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#endif
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uint32_t ref = ath_uart_freq();
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uint32_t ref = ath_uart_freq();
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uint32_t ath_cpu_freq = 0, ath_ddr_freq = 0, ath_ahb_freq = 0;
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uint32_t ath_cpu_freq = 0, ath_ddr_freq = 0, ath_ahb_freq = 0;
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@ -353,23 +355,23 @@ void ath_sys_frequency()
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clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL);
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clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL);
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pll = ath_reg_rd(ATH_PLL_CONFIG);
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pll_config = ath_reg_rd(ATH_PLL_CONFIG);
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out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll);
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out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll_config);
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ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll);
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ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll_config);
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nint = CPU_PLL_CONFIG_NINT_GET(pll);
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nint = CPU_PLL_CONFIG_NINT_GET(pll_config);
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frac = CPU_PLL_CONFIG_NFRAC_GET(pll);
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frac = CPU_PLL_CONFIG_NFRAC_GET(pll_config);
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pll = ref >> 6;
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pll_config = ref >> 6;
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frac = frac * pll / ref_div;
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frac = frac * pll_config / ref_div;
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ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
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ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
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(CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1);
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(CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1);
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pll = ath_reg_rd(ATH_DDR_PLL_CONFIG);
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pll_config = ath_reg_rd(ATH_DDR_PLL_CONFIG);
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out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll);
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out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll_config);
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ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll);
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ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll_config);
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nint = DDR_PLL_CONFIG_NINT_GET(pll);
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nint = DDR_PLL_CONFIG_NINT_GET(pll_config);
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frac = DDR_PLL_CONFIG_NFRAC_GET(pll);
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frac = DDR_PLL_CONFIG_NFRAC_GET(pll_config);
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pll = ref >> 10;
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pll_config = ref >> 10;
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frac = frac * pll / ref_div;
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frac = frac * pll_config / ref_div;
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ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
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ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) /
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(CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1);
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(CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1);
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@ -60,11 +60,11 @@ typedef struct {
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#define ath_gmac_reg_rmw_clear(_mac, _x, _y) \
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#define ath_gmac_reg_rmw_clear(_mac, _x, _y) \
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ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y))
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ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y))
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#ifdef COMPRESSED_UBOOT
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#if COMPRESSED_UBOOT
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#define _1000BASET 1000
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#define _1000BASET 1000
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#define _100BASET 100
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#define _100BASET 100
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#define _10BASET 10
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#define _10BASET 10
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#endif /* #ifdef COMPRESSED_UBOOT */
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#endif /* #if COMPRESSED_UBOOT */
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/*
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/*
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* spd is _1000BASET, _100BASET etc. defined in include/miiphy.h
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* spd is _1000BASET, _100BASET etc. defined in include/miiphy.h
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/*
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* it under the terms of the GNU General Public License version 2 and
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@ -868,8 +868,7 @@
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#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
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#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
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#define TAP_CONTROL_0_ADDRESS 0x1800001c /* Causes exception on u-boot-2016 */
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#define TAP_CONTROL_0_ADDRESS 0x1800001c
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#define TAP_CONTROL_0_ADDRESS 0xB800001c
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#define TAP_CONTROL_1_ADDRESS 0x18000020
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#define TAP_CONTROL_1_ADDRESS 0x18000020
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#define TAP_CONTROL_2_ADDRESS 0x18000024
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#define TAP_CONTROL_2_ADDRESS 0x18000024
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#define TAP_CONTROL_3_ADDRESS 0x18000028
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#define TAP_CONTROL_3_ADDRESS 0x18000028
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@ -153,20 +153,27 @@
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/*#define CONFIG_USB 1*/
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/*#define CONFIG_USB 1*/
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#if pll
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#define CFG_PLL_FREQ (pll)
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#else
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#define CFG_PLL_FREQ CFG_PLL_650_600_200
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#endif
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#define CONFIG_ATH_SOC 1
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#define CONFIG_ATH_SOC 1
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#define CONFIG_ATHEROS 1
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#define CONFIG_ATHEROS 1
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#define CONFIG_MACH_QCA953x 1
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#define CONFIG_MACH_QCA953x 1
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#define CFG_INIT_STACK_IN_SRAM 1
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#define CFG_INIT_STACK_IN_SRAM 1
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#define CONFIG_AP147 1
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#define __CONFIG_BOARD_NAME ap147
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#define __CONFIG_BOARD_NAME ap147
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#define CONFIG_BOARD_NAME "ap147"
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#define CONFIG_BOARD_NAME "ap147"
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#define BUILD_VERSION "g36c341f-dirty-1"
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#define BUILD_VERSION "g36c341f-dirty-1"
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#define CFG_PLL_FREQ CFG_PLL_650_600_200
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#define CFG_ATHRS27_PHY 1
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#define CFG_ATHRS27_PHY 1
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#define CFG_ATH_GMAC_NMACS 2
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#define CFG_ATH_GMAC_NMACS 2
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#define BOARD_NAME "AP147"
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#define BOARD_NAME "AP147"
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#define CONFIG_LAST_STAGE_INIT
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#define CONFIG_LAST_STAGE_INIT
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_CUSTOM_BOARDINFO 1
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#define CONFIG_SYS_TEXT_BASE 0x9f000000
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#define CONFIG_SYS_TEXT_BASE 0x9f000000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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