Fix regression from back when support for RTL930x was added.
While at it replace 0x8000 by BIT(15).
Fixes: 27029277f9
Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Felix Baumann <felix.bau@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20549
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl93xx_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
Adjust some details in rtl93xx_phylink_mac_config to ensure the MAC is
properly disabled MAC before configuring the SerDes. This was done
within the SerDes code before.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use regmap to access registers in the global register space so we don't
have to use the old macros sw_r32/sw_w32 anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
Import SerDes configuration code from PHY driver into the PCS driver.
Only do mandatory adjustments, rename the function to adhere to the
naming scheme, adjust all SerDes access calls.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20539
Signed-off-by: Robert Marko <robimarko@gmail.com>
In Realtek implementation USXGMII is divided in submodes:
- USXGMII_SX: 10G single link, equivalent of PHY_INTERFACE_MODE_USXGMII
- USXGMII_DX: 10G two links (2*5G ?),
- USXGMII_QX: 10G four links, presumably 4*2.5G, used with the RTL8224,
equivalent of PHY_INTERFACE_MODE_10G_QXGMII.
This CL adds the 10_GQXGMII modes to the RTL930x implementation. In
particular the "mode set" function is extended to support both simple
mode set, and force mode set depending on the mode according to
dal_longan_sds_mode_set [1].
[1] https://github.com/ddejean/dms-1250-oss-release/blob/main/sdk/sdk_rtk_switch/rtk-sdk/src/dal/longan/dal_longan_sds.c#L1746
Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20472
Signed-off-by: Robert Marko <robimarko@gmail.com>
Since ddf94f7489 and 4a5de35dba, a SerDes is configured by the PCS
driver. All code from PHY and DSA related to this has been imported and
adjusted into the PCS driver. Thus, remove the unused code from the PHY
driver now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20494
Signed-off-by: Robert Marko <robimarko@gmail.com>
L3 Offloading caused DHCP packets to be dropped at hardware level
And potentially buggy route implementation can cause a crash
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x is not supporting L3 offloading at the moment. To avoid crashes
when using this switch, simply disable L3 offloading completely.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20208
Signed-off-by: Robert Marko <robimarko@gmail.com>
Originally, phylink_mac_config first disabled the MAC, then triggered
the SerDes setup and then re-enabled MAC. SerDes setup has been moved to
the PCS driver now but pcs_config is called AFTER phylink_mac_config by
phylink subsystem.
Thus, just disable the MAC in phylink_mac_config. After PCS has setup
the SerDes, the MAC should be properly brought up in a mac_link_up call
coming from the phylink subsystem.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Remove SerDes initialization/configuration calls from the DSA driver in
'rtl931x_phylink_mac_config' and let our PCS driver setup the SerDes now
that the driver is able to do that.
pcs_config of the PCS driver is automatically called by phylink, thus
there's no need to call it on our own.
Note that in rtl931x_phylink_mac_config the MAC is enabled before
pcs_config is called. While this seems to work, it isn't good and needs
to be fixed.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In rtpcs_931x_setup_serdes, quit early on USXGMII mode. This restores
the behaviour introduced in c18476d0c5 to prevent the current buggy
procedure to destroy a working configuration established by U-Boot
before.
Also include the valuable comment from the code to keep the information.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Adjust the SerDes page numbers to account for the different mapping used
by 'mdio-realtek-otto' and 'mdio-realtek-otto-serdes' drivers.
While importing the SerDes configuration code from PHY driver to PCS
driver, all helper calls to access the SerDes registers had to be
adjusted to use the proper helpers within the PCS driver. However, there
is one important implication of this: 'mdio-realtek-otto' and
'mdio-realtek-otto-serdes' use a slightly different page mapping.
While the old helpers in 'mdio-realtek-otto' used a page mapping of
0x00/0x100/0x200, 'mdio-realtek-otto-serdes' uses a mapping of
0x00/0x40/0x80 to provide consumers with the ability to only operate on
frontend SerDes. Thus, all page numbers > 63/0x3f have to be adjusted
like the following:
before: rtsds_931x_write_field(sds, 0x101, ... // old helper calls
after: rtpcs_sds_write(ctrl, sds, 0x41, ...
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Replaces the "old" way of accessing registers using the macros
sw_r32/sw_w32 from mach-rtl83xx.h. The "new" way to access register is
through the regmap API.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Let's start this transition with RTL931X.
Import all functions starting with 'rtl931x_' or 'rtsds_931x' from PHY
driver into the PCS driver, rename all functions to match a common
naming scheme and adjust signature, helper calls and function calls
accordingly to make it work within the PCS driver.
This is just copy&paste and tries to do only mandatory adjustments. The
code will be refactored in succeeding commits.
Also remove 'unused' attribute from helpers as they are used now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20369
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA driver must flush the HW FDB when a port changes from
learning/forwarding to disabled/blocking/listening.
But the implementation for RTL931x was writing the port information
starting at bit 11 (bit 11 of the second 32-bit L2_TBL_FLUSH_CTRL
register). But this offset is the AGG_VID and not the port. The actual
position is 43 (bit 11 of the first register).
As result, the FDB was always only flushed for the port 0 and not for the
selected port.
Fixes: 9ed6097054 ("realtek: Add HW support for RTL931X for PIE, L2 and STP aging")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20422
Signed-off-by: Robert Marko <robimarko@gmail.com>
BPDU frames like STP must be processed by each switch (bridge) which
supports STP. It must not be forwarded to avoid confusing the STP state of
other STP participants. It is essential to be an active participant of STP.
The software bridge automatically takes care of forwarding the BPDUs to
other ports when STP is disabled and the hardware switch should not
interfere.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20414
Signed-off-by: Robert Marko <robimarko@gmail.com>
Right now the phylink capability function enables 2.5G and 10G modes on
Maple and Cypress, which they mostly (other than two SERDES on Cypress)
don't support. This causes these modes to be selected and break the link
as they are not supported by hardware.
I looked into doing this properly, but it cannot just be done based on
SoC, but needs to take the whole topology into account as a given MAC
might have very different capabilities depending on what SERDES are
assigned to it. So for now just use 1G and QSGMII for RTL83xx and 10G
for RTL93xx. This mostly works, except it will downgrade some 10G links
on RTL839x, but since there are also 1G SFPs on these this cannot be
solved without fully accounting for the global MAC and SERDES
configuration.
So this makes all of the 1G SFP slots work again, while keeping most of
the 10G SFP+ slots working at 10G with minimal changes.
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Link: https://github.com/openwrt/openwrt/pull/20374
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The preferred prefix for the Realtek DSA driver code is "rtldsa" and no
longer "rtl83xx". This makes sure that the different drivers have
non-conflicting prefixes and because of this non-conflicting function
names.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL930x and the RTL931x SoC families share the same struct
dsa_switch_ops. This should be represented in the name of the object.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
If two ports are in isolation mode then these ports are not supposed to be
able to communicate between each other. This can be achieved in the realtek
switch by removing the other isolated port(s) from the port list of an
isolated port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
The realtek driver is now in full control of the port matrix. It doesn't
need to rely on the current state of the HW to adjust it. The new port
matrix is calculated automatically using rtldsa_update_port_member() and
then written to the registers/tables.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
It is not necessary to read the back the current port members for a
specific port for enabling/disabling a port. All these members which are
expected to be in the HW port matrix of an active port are already stored
in the port specific member "pm".
And when a port is disabled, the port must no longer forwarding traffic to
any other port. Just writing 0 to the members is therefore good enough and
no read-back of the old HW state is necessary.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
The leave and join callbacks for DSA were using their own implementation of
the port member handling code. This makes the implementation of additional
functionality based on the port member matrix complicated because it needs
to be implemented in both places and also in the new code path for the
introduced feature.
By sharing this code, it is much easier to guarantee that all code paths
behave the same. This approach is already implemented by other DSA drivers
like qca8k, mt7530 or ksz.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20360
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a callback for a serdes setup function to rtpcs_cfg to allow each
SoC variant to define its own SerDes setup routine.
Call the setup_serdes operation in pcs_config if it is defined.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20352
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add more SerDes access helpers for the upcoming code import from PHY
driver. There, similar helpers are used to read and write full SerDes
registers or only parts of them (aka bitfields).
The helpers are expected to replace the following used in PHY SerDes
code:
- rtl9300_sds_field_r
- rtl9300_sds_field_w
- rtsds_931x_read
- rtsds_931x_read_field
- rtsds_931x_write
- rtsds_931x_write_field
Mark the helpers as unused for now to make the compiler happy. This will
be removed as soon as they are used.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20352
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are switches which share the same overall hardware design but remove
just a couple of components for the low cost variant. For example, a 8+2
(ethernet+SFP) switch might have a low cost variant which only has 8
ethernet ports. In this case, the PCB will be shared but components for SFP
will just be dropped.
The LED shift registers will be the same between the two switches but the
ports are different. But since the rtl930x_led_init code is trying to
calculate the number of LEDs using the LED ports, the ethernet status ports
will then suddenly be shifted by two ports.
It is therefore necessary to have a mechanism to overwrite the detection of
the ethernet ports in the LED initialization and force some ports to
"virtually there" for the LED controller.
This functionality was already implemented for Plasma Cloud PSX8 (RTL930x)
but some devices using RTL931x might also benefit from a similar feature.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The LED sets must be configured before per-port LEDs are actually assigned.
At the same time, the LED set configuration was basically unreadable and
the RTL930x from commit 2cfb1ecf10 ("rtl930x: Rework per port LED
configuration") does a better job. Instead of moving the old implementation
around, just adopt the one from RTL930x.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
RTL930x received support for specifying active low/high LEDs in commit
bec9e79a99 ("realtek: dsa: support active-high LEDs"). But this was
completely forgotten on RTL931x.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The usage of pr_* helper inside a device driver should be avoided. The
dev_* helper provide more context about which device the message actually
is.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The integration of the LED set initialization for RTL931x added also minor
improvements in the coding style. Just adopt them also for RTL9301x.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
of_property_count_u32_elems returns the number of u32 and not the number of
bytes. It must therefore be checked against the number of u32 in set_config
and not the bytes in set_config.
Fixes: 2cfb1ecf10 ("rtl930x: Rework per port LED configuration")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There are switches which share the same overall hardware design but remove
just a couple of components for the low cost variant. For example, a 8+2
(ethernet+SFP) switch might have a low cost variant which only has 8
ethernet ports. In this case, the PCB will be shared but components for SFP
will just be dropped.
The LED shift registers will be the same between the two switches but the
ports are different. But since the rtl930x_led_init code is trying to
calculate the number of LEDs using the LED ports, the ethernet status ports
will then suddenly be shifted by two ports.
It is therefore necessary to have a mechanism to overwrite the detection of
the ethernet ports in the LED initialization and force some ports to
"virtually there" for the LED controller.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20300
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The first RTL931x devices make their way into OpenWrt. Their copper
ports are driven by different interfaces modes like 10G_QXGMII or
Realtek proprietary XSGMII. The DSA driver has no proper handling
for theses modes implemented yet. So a lot is auto-mapped to USXGMII
internally. As soon as the SerDes setup activates this (wrong) mode
the PHY connectivity breaks.
Disable this mode for now and rely on the proper U-Boot setup.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20292
Signed-off-by: Robert Marko <robimarko@gmail.com>
If transmissions are done outside of the DSA switch (directly from the CPU
port), the STP state must not block the transmission. Otherwise, STP frames
are not correctly submitted and the STP frames cannot correctly detect
loops before switching a port in the forwarding state.
The same applies for the LLDP frames. These must be submitted independent
of the STP state to identify neighbors or configure POE limits.
It is not necessary to filter specific destination mac addresses because
the transmission was done outside the bridge/switch in the first place. The
transmission is therefore forced.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/20184
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL930X and RTL931X SoCs support port-based, flow-based, and
RSPAN-based mirroring. Like for other SoCs from the realtek target, only
the port based port mirroring can be exposed using Linux's tc subsystem.
The port_mirror_add() implementation was updated with the following
considerations for RTL93xx SoCs:
* mirrored packets must pass through the TX pipeline of the mirroring
port, so they are subject to configuration such as VLAN tagging,
remarking, and EVC
* when a packet hits both source ports (SPM) and destination port (DPM) of
a mirror group, the egress port traffic will be mirrored
The port_mirror_del() function doesn't require any modifications.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20264
Signed-off-by: Robert Marko <robimarko@gmail.com>
Instead of using a lot of if-else blocks in the port mirror code, provide
SoC specific function which calculates the SoC specific portions. The
generic part of the port mirroring code can then simply operate on the
calculated register addresses and values.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20264
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x has next to its SPI flash controller a SPI master interface. It
is connected to
* SPI_CS#[1,0]: AH22 , AK22 (aka: GPIO 12, 11)
* SPI_CLK: AL23 (aka: GPIO 8)
* SPI_MISO: AM23 (aka: GPIO 9)
* SPI_MOSI: AL22 (aka: GPIO 10)
It is not the same as the SPI flash controller which uses pins:
* SPI_CS#[1,0]: B24, A24
* SPI_SCLK: A23
* SPI_SDI/SIO0: B21
* SPO_SDO_SIO1: B21
* SPI_SIO2: A22
* SPI_SIO3: B22
* SPI_RSTN: B23
As shown above, the SPI master controller shares its pin with GPIO 8, 9,
10, 11, 12. In some upcoming devices (like the Plasma Cloud PSX28/ESX28),
they will be used for SFP cage signaling. These pins must therefore be
switched manually to the GPIO mode.
The SPI_CTRL0 register provides all necessary configuration to enforce the
GPIO mode of the pins. And until more requirements (and a correct driver)
for the SPI master controller arise, it is therefore possible to use
pinctrl-single to configure it using the devicetree.
Previously the ethernet driver did configure the SPI master controller for
31.25 MHz. It is unknown for which kind of device this was originally made
and what was actually connected there. But this manual write to the
register conflicts potentially with the write of the pinctrl driver to the
same register. Luckily, we don't need this SPI speed configuration in the
ethernet driver. Still, to allow this device an easy migration, the
`spi0-31mhz` configuration was already prepared.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20263
Signed-off-by: Robert Marko <robimarko@gmail.com>
The current SerDes implementation for RTL931x handles 10G-QXGMII via the
"usxgmii" PHY mode. This is not 100% correct because it is not a single
port with 10G (max) but 4 ports with 2.5G each.
To allow setting of the "10g-qxgmii" phy mode, just change the code for now
to use the same codepaths as USXGMII. This has to be cleaned up further
during the SerDes driver rewrites.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20239
Signed-off-by: Robert Marko <robimarko@gmail.com>
During testing, we discovered that when adding a new offload FDB rule
on certain VLANs and then delete it, does not work as expected.
Steps to Reproduce:
* Create VLAN 4094 on the port lan1:
bridge vlan add vid 4094 dev lan1 pvid
* Add a new FDB entry on port lan1 for VLAN 4094:
bridge fdb add 00:01:02:22:33:44 dev lan1 vlan 4094 master permanent
* Delete the new FDB entry on port lan1 for VLAN4094
bridge fdb del 00:01:02:22:33:44 dev lan1 vlan 4094 master permanent
Root Cause:
The failure occurs because the hash_msb flag is not set correctly
based on the VLAN ID when adding a new L2 entry.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20183
Signed-off-by: Robert Marko <robimarko@gmail.com>
Parse the pcs-handle property regardless of phy-handle
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/20228
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are SFP modules which only work if auto-negotiation is disabled,
like some "OEM SFP-2.5G-T" modules. This also seems to be necessary for
RTL8226/RTL8221B PHYs when using 2500Base-X.
However, currently, it is always enabled, so add support for configuring
it to make these SFP modules and PHYs work.
This also adds locking which should be useful for future extension of
the PCS driver.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19518
Signed-off-by: Robert Marko <robimarko@gmail.com>
In the Realtek dts the pcs-handle property at the switch port is the
successor of the sds property at the phy. Rearrange the MDIO and DSA
driver so they always look at the new attribute.
Remark! This code can be dropped completely if the new PCS driver
is fully featured. But this will take some time.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20148
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that there is a dedicated PCS driver remove the old functions
from the DSA driver and make use of the new ones.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20129
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Until now the the SerDes configuration is realized with helper functions
scattered around the DSA and PHY driver. Give them a new home as a PCS
driver.
The target design is as follows:
- dsa driver manages switch
- pcs driver manages SerDes on high level (this commit)
- mdio driver manages SerDes on low level
This driver adds the high level SerDes access via PCS. It makes use of
the low level mdio SerDes driver to access the registers.
Remark: This initial version provides exactly all phylink_pcs_ops that
are currently part of the DSA driver. So this can be swapped in one of
the next commits as a drop in replacement. To make use of it something
like this is needed:
...
ports = of_get_child_by_name(node, "ethernet-ports");
if (!ports)
return -EINVAL;
for_each_available_child_of_node(ports, port) {
pcs_node = of_parse_phandle(port, "pcs-handle", 0);
of_property_read_u32(port, "reg", &port_nr)) {
priv->pcs[port_nr] = rtpcs_create(dev, pcs_node, port_nr);
}
...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20075
Signed-off-by: Robert Marko <robimarko@gmail.com>
The upcoming PCS driver will lookup the SerDes mdio bus via
of_mdio_find_bus() and the devicetree. This is only possible
with proper registration via devm_of_mdiobus_register().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20078
Signed-off-by: Robert Marko <robimarko@gmail.com>
