After the recent change pipelining over three DMA transfers,
we obviously need two different idle line buffers, otherwise
the the metadata in the idle line currently in flight will
be overwritten in case we have two idle lines in a row.
When utilizing the full data rate, this cannot be observed,
as there won't be two idle lines in a row.
Previously when using an HSTX clock > sysclk/2,
there was a DMA underrun from time to time,
which limited the achievable data rate to
around 75 MByte/s. By using a third DMA channel
and employing some trickery to be still able to
use the DMA CRC sniffer, we now can achieve
128 MByte/s (or even more) by using sysclk/1
as HSTX clock.
The counter example has been updated to
generate those ~128 MByte/s.
