Steve Markgraf 040bdb24a4 Optimize async FIFO critical path and add CLI build system ... Replace chained adder in rptr_empty/wptr_full with parallel pre-computation (rbin+1, rbin+2) and mux selection. This reduces the critical path from ~9 to ~5-6 logic levels, improving clk_pixel Fmax from 120.8 to 166.7 MHz (+38%). Add build.sh/build.tcl for headless CLI builds via gw_sh with timing-driven PnR and increased placement/routing effort. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>		2026-03-07 23:37:22 +01:00
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async_fifo	Optimize async FIFO critical path and add CLI build system	2026-03-07 23:37:22 +01:00
hdmi	Fix Verilog coding style and add proper SDC timing constraints	2026-03-07 22:20:39 +01:00
hsdaoh	Fix Verilog coding style and add proper SDC timing constraints	2026-03-07 22:20:39 +01:00