Steve Markgraf 97f0c4ffd1 Fix Verilog coding style and add proper SDC timing constraints ... Fix blocking/non-blocking assignment mismatches: use = in combinational blocks (hdmi.v hsync/vsync) and <= in sequential blocks (hsdaoh_core.v fifo_read_en). Add explicit PLL clock definitions and asynchronous clock group declarations to all SDC files to eliminate false cross-domain timing violations. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>		2026-03-07 22:20:39 +01:00
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crc16_ccitt.v	hsdaoh_core: add CRC16 checksum support	2024-12-06 22:57:41 +01:00
hsdaoh_core.v	Fix Verilog coding style and add proper SDC timing constraints	2026-03-07 22:20:39 +01:00