Steve Markgraf 97f0c4ffd1 Fix Verilog coding style and add proper SDC timing constraints ... Fix blocking/non-blocking assignment mismatches: use = in combinational blocks (hdmi.v hsync/vsync) and <= in sequential blocks (hsdaoh_core.v fifo_read_en). Add explicit PLL clock definitions and asynchronous clock group declarations to all SDC files to eliminate false cross-domain timing violations. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>		2026-03-07 22:20:39 +01:00
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auxiliary_video_information_info_frame.v	initial commit	2024-05-05 01:03:12 +02:00
hdmi.v	Fix Verilog coding style and add proper SDC timing constraints	2026-03-07 22:20:39 +01:00
packet_assembler.v	initial commit	2024-05-05 01:03:12 +02:00
packet_picker.v	initial commit	2024-05-05 01:03:12 +02:00
serializer.v	initial commit	2024-05-05 01:03:12 +02:00
tmds_channel.v	hdmi: switch to pipelined TMDS encoder	2024-12-07 23:44:30 +01:00