7e9afe21f5
Refactor hsdaoh_core.v to support multiple data modes via parameters: - DSIZE: FIFO data width (default 16) - PACK_MODE: 0=passthrough, 1=10-bit IQ (20→16), 2=12-bit dual (24→16) - FORMAT_ID: 12-bit identifier for data format - USE_CRC: enable/disable CRC (default 1) - pack_enable input for runtime control of bit packing Add nano20k_sdr project (10-bit IQ ADC with dynamic PLL, UART/I2C bridge). Add nano9k_dualadc project (dual 12-bit ADC with div3 clock). Add common/uart_i2c_bridge and common/div3.v modules. Add SSPI-as-GPIO option to build.tcl for SDR pin constraints. All existing test projects updated with .pack_enable(1'b0) - no functional change. All projects verified building with 0 timing violations. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> |
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|---|---|---|
| common | ||
| hsdaoh_nano4k_test | ||
| hsdaoh_nano9k_dualadc | ||
| hsdaoh_nano9k_test | ||
| hsdaoh_nano20k_sdr | ||
| hsdaoh_nano20k_test | ||
| hsdaoh_primer20k_test | ||
| hsdaoh_primer25k_test | ||
| .gitignore | ||
| build.sh | ||
| build.tcl | ||
| hsdaoh_nano4k_test.gprj | ||
| hsdaoh_nano4k_test.gprj.user | ||
| hsdaoh_nano9k_dualadc.gprj | ||
| hsdaoh_nano9k_test.gprj | ||
| hsdaoh_nano9k_test.gprj.user | ||
| hsdaoh_nano20k_sdr.gprj | ||
| hsdaoh_nano20k_test.gprj | ||
| hsdaoh_nano20k_test.gprj.user | ||
| hsdaoh_primer20k_test.gprj | ||
| hsdaoh_primer20k_test.gprj.user | ||
| hsdaoh_primer25k_test.gprj | ||
| hsdaoh_primer25k_test.gprj.user | ||
| LICENSE | ||
| README.md | ||
FPGA implementation of hsdaoh - High Speed Data Acquisition over HDMI
This repository contains the FPGA implementation and example designs for the Tang Nano/Primer series of FPGA boards. For more information see the main repository.
The example design generates a 16 bit counter, that then can be verified on the host. With a small modification to the clk_data process in the top-file of your respective FPGA board you can stream your own payload data.
Building the desgin
Currently, the bitfiles must be generated with the GOWIN IDE (V1.9.11.03 Education). See here for more information on how to set up the IDE.
For launching on Arch Linux:
rm ./IDE/lib/libfreetype.so.6
LD_LIBRARY_PATH=./IDE/lib/ ./IDE/bin/gw_ide
In the future, it might be possible to use the Open Source toolchain (Yosys + nextpnr-himbaechel + apicula). This is currently blocked by the lack of the CLKDIV primitive in the Open Source tools.
Loading the bitfile
The bitfile can be either loaded with the GOWIN Programmer, or with openFPGALoader.
Here is an example commandline for loading the bitfile on a Tang Nano 20K:
openFPGALoader -b tangnano20k hsdaoh_nano20k_test.fs
Testing the design
After loading the bitfile, connect the FPGA board to a MS2130 HDMI grabber and confirm that the video output is working. You then can use hsdaoh_test to verify the counter values.
Credits
The hsdaoh FPGA design was developed by Steve Markgraf, and is heavily based on the HDMI IP core by Sameer Puri and also uses the asynchronous FIFO by Damien Pretet.