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master

c03f45e226 · update for newer Gowin IDE · Updated 2025-11-29 01:12:07 +01:00
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claude

7e9afe21f5 · Integrate SDR and dual-ADC projects with parameterized hsdaoh_core · Updated 2026-03-08 23:26:28 +01:00
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nano9k_dualadc

1339c06b11 · add Tang nano 9K dual 12 bit ADC project · Updated 2025-03-24 23:36:17 +01:00    mirror

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yosys

2bfe1c635a · WIP: first test with yosys/nextpnr/apicula · Updated 2024-07-12 21:13:09 +02:00    mirror

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sdr

1ccf7399b8 · import hsdaohSDR FPGA design · Updated 2024-05-27 00:43:57 +02:00    mirror

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