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hsdaoh-fpga/common
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Steve Markgraf 7e9afe21f5 Integrate SDR and dual-ADC projects with parameterized hsdaoh_core 
Refactor hsdaoh_core.v to support multiple data modes via parameters:
- DSIZE: FIFO data width (default 16)
- PACK_MODE: 0=passthrough, 1=10-bit IQ (20→16), 2=12-bit dual (24→16)
- FORMAT_ID: 12-bit identifier for data format
- USE_CRC: enable/disable CRC (default 1)
- pack_enable input for runtime control of bit packing

Add nano20k_sdr project (10-bit IQ ADC with dynamic PLL, UART/I2C bridge).
Add nano9k_dualadc project (dual 12-bit ADC with div3 clock).
Add common/uart_i2c_bridge and common/div3.v modules.
Add SSPI-as-GPIO option to build.tcl for SDR pin constraints.
All existing test projects updated with .pack_enable(1'b0) - no functional change.
All projects verified building with 0 timing violations.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-08 23:26:28 +01:00
..
async_fifo Optimize async FIFO critical path and add CLI build system 2026-03-07 23:37:22 +01:00
hdmi Fix Verilog coding style and add proper SDC timing constraints 2026-03-07 22:20:39 +01:00
hsdaoh Integrate SDR and dual-ADC projects with parameterized hsdaoh_core 2026-03-08 23:26:28 +01:00
uart_i2c_bridge Integrate SDR and dual-ADC projects with parameterized hsdaoh_core 2026-03-08 23:26:28 +01:00
div3.v Integrate SDR and dual-ADC projects with parameterized hsdaoh_core 2026-03-08 23:26:28 +01:00