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https://github.com/steve-m/hsdaoh-fpga.git
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040bdb24a4
Replace chained adder in rptr_empty/wptr_full with parallel pre-computation (rbin+1, rbin+2) and mux selection. This reduces the critical path from ~9 to ~5-6 logic levels, improving clk_pixel Fmax from 120.8 to 166.7 MHz (+38%). Add build.sh/build.tcl for headless CLI builds via gw_sh with timing-driven PnR and increased placement/routing effort. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
86 lines
2.7 KiB
Verilog
86 lines
2.7 KiB
Verilog
// https://github.com/dpretet/async_fifo
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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// Optimized: replaced chained adder (rbin+inc then +1) with parallel
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// pre-computation of rbin+1 and rbin+2, selected via mux. This reduces
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// the arempty critical path from ~9 to ~5-6 logic levels.
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`timescale 1 ns / 1 ps
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`default_nettype none
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module rptr_empty
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#(
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parameter ADDRSIZE = 4
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)(
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input wire rclk,
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input wire rrst_n,
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input wire rinc,
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input wire [ADDRSIZE :0] rq2_wptr,
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output reg rempty,
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output reg arempty,
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output wire [ADDRSIZE-1:0] raddr,
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output reg [ADDRSIZE :0] rptr
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);
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reg [ADDRSIZE:0] rbin;
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wire [ADDRSIZE:0] rgraynext, rbinnext;
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wire arempty_val, rempty_val;
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// Pre-compute incremented values from registered rbin (parallel, not chained)
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wire [ADDRSIZE:0] rbin_p1 = rbin + 1'b1;
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wire [ADDRSIZE:0] rbin_p2 = rbin + 2'd2;
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wire do_read = rinc & ~rempty;
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// Gray code conversions from pre-computed values
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wire [ADDRSIZE:0] rgray_p1 = (rbin_p1 >> 1) ^ rbin_p1;
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wire [ADDRSIZE:0] rgray_p2 = (rbin_p2 >> 1) ^ rbin_p2;
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// Select based on whether a read is happening this cycle
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// When do_read: rbinnext = rbin+1, rgraynext = gray(rbin+1)
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// When !do_read: rbinnext = rbin, rgraynext = gray(rbin) = rptr (already registered)
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assign rbinnext = do_read ? rbin_p1 : rbin;
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assign rgraynext = do_read ? rgray_p1 : rptr;
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// "Almost empty" = will be empty after one more read from projected next position
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// rgraynextm1 = gray(rbinnext + 1) = gray(do_read ? rbin+2 : rbin+1)
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wire [ADDRSIZE:0] rgraynextm1 = do_read ? rgray_p2 : rgray_p1;
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//-------------------
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// GRAYSTYLE2 pointer
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//-------------------
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always @(posedge rclk or negedge rrst_n) begin
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if (!rrst_n)
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{rbin, rptr} <= 0;
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else
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{rbin, rptr} <= {rbinnext, rgraynext};
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end
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// Memory read-address pointer (okay to use binary to address memory)
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assign raddr = rbin[ADDRSIZE-1:0];
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//---------------------------------------------------------------
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// FIFO empty when the next rptr == synchronized wptr or on reset
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//---------------------------------------------------------------
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assign rempty_val = (rgraynext == rq2_wptr);
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assign arempty_val = (rgraynextm1 == rq2_wptr);
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always @ (posedge rclk or negedge rrst_n) begin
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if (!rrst_n) begin
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arempty <= 1'b0;
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rempty <= 1'b1;
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end
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else begin
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arempty <= arempty_val;
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rempty <= rempty_val;
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end
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end
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endmodule
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`resetall
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