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hsdaoh-fpga/common/async_fifo
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Steve Markgraf 040bdb24a4 Optimize async FIFO critical path and add CLI build system 
Replace chained adder in rptr_empty/wptr_full with parallel
pre-computation (rbin+1, rbin+2) and mux selection. This reduces
the critical path from ~9 to ~5-6 logic levels, improving clk_pixel
Fmax from 120.8 to 166.7 MHz (+38%).

Add build.sh/build.tcl for headless CLI builds via gw_sh with
timing-driven PnR and increased placement/routing effort.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-07 23:37:22 +01:00
..
async_fifo.v initial commit 2024-05-05 01:03:12 +02:00
fifomem.v initial commit 2024-05-05 01:03:12 +02:00
rptr_empty.v Optimize async FIFO critical path and add CLI build system 2026-03-07 23:37:22 +01:00
sync_r2w.v initial commit 2024-05-05 01:03:12 +02:00
sync_w2r.v initial commit 2024-05-05 01:03:12 +02:00
wptr_full.v Optimize async FIFO critical path and add CLI build system 2026-03-07 23:37:22 +01:00