mirror of
https://github.com/steve-m/hsdaoh-fpga.git
synced 2026-03-14 21:09:46 +01:00
7e9afe21f5
Refactor hsdaoh_core.v to support multiple data modes via parameters: - DSIZE: FIFO data width (default 16) - PACK_MODE: 0=passthrough, 1=10-bit IQ (20→16), 2=12-bit dual (24→16) - FORMAT_ID: 12-bit identifier for data format - USE_CRC: enable/disable CRC (default 1) - pack_enable input for runtime control of bit packing Add nano20k_sdr project (10-bit IQ ADC with dynamic PLL, UART/I2C bridge). Add nano9k_dualadc project (dual 12-bit ADC with div3 clock). Add common/uart_i2c_bridge and common/div3.v modules. Add SSPI-as-GPIO option to build.tcl for SDR pin constraints. All existing test projects updated with .pack_enable(1'b0) - no functional change. All projects verified building with 0 timing violations. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
29 lines
535 B
Verilog
29 lines
535 B
Verilog
module clk_div3(clk,reset, clk_out);
|
|
|
|
input clk;
|
|
input reset;
|
|
output clk_out;
|
|
|
|
reg [1:0] pos_count, neg_count;
|
|
wire [1:0] r_nxt;
|
|
|
|
always @(posedge clk) begin
|
|
if (reset)
|
|
pos_count <= 0;
|
|
else if (pos_count == 2)
|
|
pos_count <= 0;
|
|
else
|
|
pos_count <= pos_count + 1;
|
|
end
|
|
|
|
always @(negedge clk) begin
|
|
if (reset)
|
|
neg_count <=0;
|
|
else if (neg_count == 2)
|
|
neg_count <= 0;
|
|
else
|
|
neg_count<= neg_count +1;
|
|
end
|
|
|
|
assign clk_out = ~((pos_count == 2) | (neg_count == 2));
|
|
endmodule
|