RTL93xx devices can no longer find the switch node in the DTS.
Commit 4c92254 ("relocate/retype switch node") refactored the
switch node definition to better align with upstream. Sadly
the redefinition for RTL93xx devices failed.
- RTL83xx: use "switch0: ethernet-switch"
- RTL93xx: use "switch0: switch@1b000000"
Follow up commit 8b969f7 ("drop realtek,smi-address property)
changed the dts lookup sequence for mdio initialization. On
RTL93xx devices it cannot find the switchnode via
of_get_child_by_name(dev->of_node->parent, "ethernet-switch")
Fix the switch node type for RTL93xx
Fixes: 8b969f7 ("drop realtek,smi-address property)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22557
Signed-off-by: Robert Marko <robimarko@gmail.com>
During RX calibration we use a vth_min value of 0 while the SDK always
uses a value of 1 [1]. While we do not know right now which effect this
really has, sync this to the SDK. In worst case we might have an
insufficient calibration result at the moment which usually might be
fine.
[1] 82af3a36b7/sources/rtk-dms1250/src/dal/longan/dal_longan_sds.c (L173)
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
The order within the FGCAL code is not optimal. Right now, there's
output printed even in successful cases (which doesn't really help) and
a value is read although it isn't used if the run succeeds. To fix both,
move that below the success loop exit so it's just printed in
non-success case where the information might be helpful.
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Simplify some register writes being different for even and odd SerDes by
removing if-else and use ternary operator instead. This makes code
shorter and more readable.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Comparing our calibration check with the one in the SDK ([1]), one can
see some discrepancies for which there are no apparent reasons. SGMII
and 1000Base-X are handled equal to XSGMII although they aren't in the
SDK and have different symbol error registers. USXGMII and 10GBase-R are
fine, but other modes are explicitly handled with failure then.
Restructure this by keeping XSGMII alone with its dedicated check (as
the SDK does) and handle all other modes differently. Though the SDK
just skips symbol error check for modes like SGMII, 1000Base-X,
2500Base-X, it was found to be ok to perform a simple check for them
too. Since we have also a default case in the symbol error read
implementation now, we can cover all other modes with default case here
too. As a side-effect, this removes the confusing and probably wrong
failure stating calibration has failed although just the checks were
insufficient.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Our implementation waiting for RX idle signal of a 10G SerDes deviates
from what the SDK does. While we timeout after 100 reads and thus cannot
really control the real time, the SDK times out after 10ms. Adjust that
accordingly by switching the timeout to ktime_* functions with a 10ms
timeout as per the SDK.
While at it, improve the overall style of the function a bit.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the symbol error read implementation to be usable for other modes
too. While we handle other modes as 'not supported', the SDK has a
generic read used in the 'default' case. Do the same so we can have
proper 2500Base-X support here and avoid confusing error messages.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Instead of performing a dedicated register read we can rely on the mode
that is passed via a parameter to the function. The code flow ensures
that this is the same value in this place.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Part of the calibration procedure contains some weird and harebrained
piece of code where a specific register write is guarded by a check for
the SerDes mode, otherwise an error is printed. But right after this
if-else block, the exact same write is applied anyway. Remove this
brain-dead piece of code with something meaningful, i.e. reference code
from the SDK [1]. Over there, more writes are applied and a proper check
is in place.
While at it, add some another comment to the code. While it is
honourable to have code developed by someone quite some time ago that
works, it's discouraged to just have code without any explanation
especially if it differs from the SDK.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Calibration for RTL930x uses multiple iterations for several checks.
While this is fine and needed, it shouldn't be allowed to run forever in
trust that at some point there will always be a "valid" value causing a
loop exit. This has occured a couple of times, causing the driver to
loop forever in case something doesn't run as expected.
To avoid this (and in general as a good practice) limit the affected
loop to a rough estimate of 10 iterations instead of running possibly
forever. The estimate is based on the fact that under normal conditions
it usually takes 1 or 2 to iterations to succeed, more is likely never
to succeed but 10 gives some reasonable headroom.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Cleanup some comments in the code by reducing them to the essential and
putting them behind a line in favor of above. Also simplify some output
prints for the same purpose.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
A phy node in the dts has two properties:
- reg: the (overall) address of the phy
- realtek,smi-address: the address of the phy on its bus
This notation does not align with upstream. reg should be the address
of the phy on its bus. But where to get the overall address that is
needed for register writes to the hardware?
Luckily the mdio driver and the hardware design sync the ports and
phys (overall) addresses. Thus derive missing data from the dts port
nodes (below ethernet-ports). To realize this
- carve out the port mapping into a separate function to align with
the upstream driver.
- do more sanity checks and catch more inconsistencies
- raise more/better errors via dev_err_probe()
With this commit all dts files must be rewritten as follows:
- if phy has no realtek,smi-address leave it as is
- if phy has realtek,smi-address, write that value into the reg
property and drop realtek,smi-address.
Remark: This commit might bring some confusion about the phyXX and
phy@YY and <reg=YY> naming convention. To be somehow consistent with
the current port/phy identifiers from now on the dts will have:
- phyXX: where XX matches the port number
- phy@YY: where YY is the phy address on the mdio bus
- <reg=YY>: where YY is the phy address on the mdio bus
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The switch node is currently located outside of the switchcore@1b000000
tree. This makes it hard to find when referencing from other nodes in
this tree. Make it a subnode of switchcore and "retype" it to
ethernet-switch like upstream does.
This is not perfectly aligned as upstream just mixes the switchcore and
the ethernet-switch node into one. But this will be future work for
downstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The Zyxel XGS1x10 DTS overzealously tries to avoid redundancies. For
this the phy24/phy25 definitions were split into a common and a device
specific part. Understanding how these phys are defined is therefore
a little bit tricky. Add a little bit of redundancy to make the
definitions easier to read and understand in a single location.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This commit adds support for RTL9607C/RTL8198D clocks to the existing
clk-rtl83xx driver. Setting clock rates is not supported due to
lack of knowledge on this topic at the moment. Clocks for CPU1, SRAM
and SPI can also be calculated but not included in this commit.
Since the registers, calculations are widely different to RTL83XX it
was decide to have different clk_ops for RTL960X.
The code was partly based on naseef's work with some changes to
integrate it into the clk-rtl83xx driver.
Tested-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22080
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for RTL9607C / RTL8198D thermal controller.
Based on the Realtek SDK code.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22081
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL8226 PHYs in Zyxel XGS1010-10 and XGS1210-10 rev A1 have swapped
MDI lanes. Specify this in the device tree, so the driver can configure
it. With this change, the PHYs no longer require initialization by the
bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The PHY supports swapping the MDI pairs (ABCD->DCBA) to simplify board
layout. On devices making use of this, it needs to be configured in the
driver, otherwise the PHY won't work properly.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The dsa irq handler works always in the same way for all SoCs.
- Read register ISR_PORT_LINK_STS_CHG to determine the ports that
triggered the irq.
- Write the read value back to the register to confirm the irq
- Read link status via MAC_LINK_STS
- Trigger dsa_port_phylink_mac_change() for each changed port
Currently each SoC has its own implementation. Drop that in
favour of a generic implementation that makes use of the existing
bit register read/write helpers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22273
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This register will be needed to provide a generic irq handler. Add
it to the configuration structure of the driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22273
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some 10G optics showed random "module transmit fault indicated" due to I2C
read errors on ONTi ONT-S508CL-8S/XikeStor SKS8300-8X switches. The same
modules work with the original firmware and on other Linux based devices.
There seems to be some differences in how we talk to those modules using
I2C in OpenWRT. To fix this this patch adds support for 50kHz I2C speed on
SFPs and enables that for XikeStor/Onti devices. Since SFPs only transmit
very few bytes this should not have any real downsides.
This patch configures I2C to use 50kHz clock in the DTS for the affected
devices. For it to work it requires a change in the RTL9300 I2C driver.
This can be safely merged without the kernel change (but will not work
in that case as it will fall back to 100kHz).
Signed-off-by: Jan Kantert <jan-openwrt@kantert.net>
Link: https://github.com/openwrt/openwrt/pull/22210
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The current CMU setup was just copied and slightly adjusted from the
SDK, lacks functionality and logic and doesn't cover all cases we need
(same in the SDK due to multiple reasons). The existing implementation
for RTL930x covers all that and can be reused for RTL931x. Previous
patches made this generic and now we can add the remaining missing
pieces to actually use it for RTL931x. This only includes
implementations for the few variant-specific actions within the
implementation, linking them properly and calling the CMU configuration.
Drop the old CMU code for RTL931x then since it's not needed anymore.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Improve the RTL931x mapper to infer the CMU page from the hardware mode
by replace unneeded with useful comments, returning a better error code
and dropping irrelevant parts.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Do some slight improvements to the generic CMU configuration for
RTL93xx. This covers several points:
- update comments to the current reality
- add fast path to avoid issues and unneeded calls
- use cached mode value instead of register read
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Generalize the RTL930x CMU configuration to support RTL931x as well.
Both implementations differ only in minor details, allowing them to
share common code and avoid duplication.
Affected functions are moved up in the code to the 93xx common area and
slightly renamed. Existing variant-specific functions are adjusted too
and assigned to the previously added SerDes operation hooks.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add new SerDes ops for CMU management to be able to share common
behavior of CMU configuration for RTL930x and RTL931x while still
covering variant specifics.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Fix naming of several functions to better reflect what they are doing.
While at it, also improve the error handling a lot, changing the return
type from void to int and actually returning errors.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move resetting the CMU into the PLL configuration itself where the speed
is set. Since this operation is not dependent of the target SerDes and
only needs to be called if the speed changed, it fits better there.
Though the call was guarded with a 'speed_changed' before, this also
applies to actually changing the speed. This was done before anyway,
even if the speed value hasn't really changed.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add a mapper function to infer the to-be-selected PLL speed from the
desired SerDes hardware mode. This avoids having similar logic in each
CMU implementation.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Split up PLL configuration of RTL930x in the two distinct actions of
configuring the PLL itself (aka setting its speed, etc.) and selecting
which PLL is used by a SerDes.
It was found that for both RTL930x and RTL931x, PLL configuration can be
combined while selecting the PLL a SerDes uses differs and needs to be
implemented variant-specific.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make use of the generic PLL type definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the fields of
the PLL type enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.
Selecting the PLL to use for a SerDes shares some similarities between
RTL930x and RTL931x. While the location of the selector in the registers
is placed different, similar underlying bit semantics are used. This
allows to reuse the same plain values for both. RTL930x uses a force bit
and a selector bit, RTL931x at least uses the selector bit with the same
values for ring and LC PLL.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make use of the generic PLL speed definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the field of
the PLL speed enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.
Setting the actual speed selector for RTL930x was found to be similar to
RTL931x despite of different values being used since the LSB is always 1.
According to the SDK this seems to be a force bit while the other bits
are the actual value/selector that is being forced. For RTL930x,
separate the speed selection to be able to use that as common behavior
for both variants later.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Bring the PLL definitions into a proper shape. While there was already a
definition for the PLL type, a generic PLL speed definition was missing.
Introduce such a definition and adjust the naming of the existing PLL
type definition to have a better distinction and avoid conflicts. The
definitions can and should be used to make the CMU/PLL configuration
more generic and reduce the need for variant-specific definitions.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22198
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ethernet driver configures the SoC internal network card
on its own. There are no special serdes or other layers in
between. So there is no need for pcs handling in the driver.
Drop that.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22347
Signed-off-by: Robert Marko <robimarko@gmail.com>
These devices contain a single MAC address in the U-Boot environment.
Set it as eth0 and label MAC in device tree. To maintain the current
state, the 02_network script still sets individual port MAC addresses
and the bridge MAC address.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22302
Signed-off-by: Robert Marko <robimarko@gmail.com>
Allow to convert MAC adddresses for all devices to NVMEM in
the future.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22302
Signed-off-by: Robert Marko <robimarko@gmail.com>
In generic, there's a backport from 6.14 that makes this change. Do so
in downstream locations as well.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21167
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL838x devices cannot reboot if the flash controller is driven in
4 byte mode. Unitl fdc3776 ("realtek: pcs: fix PLL_CML_CTRL for
serdes 0/1") this bit was luckily cleared by a coding error. Since
then the device cannot be rebooted anymore.
Looking at the SDK one can see that this bit is reset short before
the reboot happens. But we might need that in critical situations
where there is no chance to do it right in time. As the RTL838x
always ran with the bit disabled restore the old behaviour. This
time implement it as a documented quirk so it does not get lost.
Fixes: fdc3776 ("realtek: pcs: fix PLL_CML_CTRL for serdes 0/1")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22334
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Realtek DSA driver accesses the DTS at two locations.
- rtldsa_ethernet_loaded(): to check if ethernet driver is active
- rtl83xx_mdio_probe(): to create ports and link to pcs/phy
The first function does not directly search for the ethernet driver
but looks it up through the switch port nodes. Avoid future issues
and simply search all nodes that have a "ethernet" link to the
network driver.
While we are here add a missing put_device() to keep reference
counters clean.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22235
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
rteth_930x_create_tx_header() and rteth_931x_create_tx_header() do
basically the same. Only exception is, that one function can handle
ports beyond 32 and the other not. Merge them into one.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22228
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
MAC setting uses hard to read duplicated code. Additionally it
evaluates the unwanted family_id attribute. Provide the list
of MAC address registers in the configuration structure and use
a loop to fill those.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22217
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There is a workaround in the transmit path for the RTL838x SoCs. This
is basically an open coded read_poll_timeout() and makes the code hard
to read. Additionally the magic trigger calculation is not easy to
understand.
Simplify things by using kernel standards and a better macro.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22217
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some 10G optics showed random "module transmit fault indicated" due to I2C
read errors on ONTi ONT-S508CL-8S/XikeStor SKS8300-8X switches. The same
modules work with the original firmware and on other Linux based devices.
There seems to be some differences in how we talk to those modules using
I2C in OpenWRT. To fix this this patch adds support for 50kHz I2C speed on
SFPs and enables that for XikeStor/Onti devices. Since SFPs only transmit
very few bytes this should not have any real downsides.
This patch adds support in the i2c driver for 50kHz and 2.5MHz. In a
second PR I will configure 50kHz in the DTS for the affected devices.
Signed-off-by: Jan Kantert <jan-openwrt@kantert.net>
Link: https://github.com/openwrt/openwrt/pull/22209
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
LACP frequently changes active/backup links. driver must also handle
dp->lag_tx_enabled.
This should only affect egress LAG table, ingress should not be touched.
To test, connect a known working 802.3ad compatible switch (Mikrotik).
Configure bond with 802.3ad on openwrt as well as mikrotik.
Observer active/backup links on openwrt with
```
for iface in <list of bond participants>; do
ip -d link show $iface
done
```
This should show ACTIVE/BACKUP status which must be synchronized with
the partner's ACTIVE/BACKUP status if LACP is working correctly.
Backup interface must not be chosen by the distribution algorithm to
transmit egress packet
At the moment, we have two parties involved in the selection of active LAG TX
ports:
- the bonding/DSA code which informs about activated/deactivated ports using
.port_lag_change
- the HW which is deactivating ports based on the link state see
RTL93XX_TRK_CTRL_LINK_DOWN_AVOID
In our case, the software is supposed to manage everything
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
With this commit it is possible to create 802.3ad compatible bond
interface that is interoperable with other 802.3ad compatible switches.
Each trunk group can have maximum of 8 ports as members.
Hardware also supports trunking with stacked switches, however it is not
handled here and the driver only configures the local trunk.
rtl930x and rtl931x has minimal differences in trunk/lag
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
rtl93xx has two distribution algorithm slots that are shared among
multiple trunks.
Each of this slot can be configured to handle L2 and/or L3 packets
Hardware can also be configured to support layer3+4 but that is not
802.3ad compliant. With this commmit I want to focus on getting
layer2 and layer2+3 initialized in two slots.
When a new LAG group is created, depending on the xmit_hash_policy
configuration a slot will be configured in LAG table entry
SPA and VLAN bits made the switch to always choose same link for all
connections which completely dismisses point of Link aggregation.
So avoid these and stick to SMAC + DMAC for L2 packets and
SMAC + DMAC + SIP + DIP for L3 packets
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Jan Fuchs <jf@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
rtl93xx hardware supports trunk fdb entries. That requires driver to
translate port-fdb entry to trunk fdb entry if the port is part of a
LAG.
There is no standard way of indicating fdb entries for bond interfaces.
One can use debugfs interface l2_table to dump all the entries stored in
the hardware. Trunk FDB entries are now displayed properly with trunk ID
and participating ports
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
rtl9310 and rtl9300 have two slots for configuration of packet distribution
algorithm that can be assigned to multiple LAG groups. They also have the
same field descriptions
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
It is not helpful at the moment to expose all the SoC specific details to
the common code when it actually only needed to add ports to a LAG. Just
have a simple interface for now.
Support returning errors while setting distribution algorithm
Move setting algomask to rtl83xx specific routine and out of common lag_add
because algomasks will be handled differently on rtl93xx
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/21740
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add pending patch for improving Huawei MA5671a SFP fixup, which allows
communicating with the module even if the fiber isn't connected.
Link: https://github.com/openwrt/openwrt/pull/22283
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
