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realtek: dts: normalize Zyxel XGS1x10 DTS

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The Zyxel XGS1x10 DTS overzealously tries to avoid redundancies. For
this the phy24/phy25 definitions were split into a common and a device
specific part. Understanding how these phys are defined is therefore
a little bit tricky. Add a little bit of redundancy to make the
definitions easier to read and understand in a single location.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This commit is contained in:
Markus Stockhausen 2026-03-09 10:50:44 +01:00 • committed by Robert Marko
parent 04308ad284
commit f5ec3f2df2
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GPG key ID: 66D805C09F36AFA5
4 changed files with 40 additions and 34 deletions
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20
target/linux/realtek/dts/rtl9302_zyxel_xgs1010-12-a1.dts
View file

@ -103,12 +103,20 @@
};
};
&phy24 {
realtek,smi-address = <8>;
enet-phy-pair-order = <1>;
&mdio_bus1 {
phy24: ethernet-phy@24 {
reg = <24>;
realtek,smi-address = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
};
&phy25 {
realtek,smi-address = <9>;
enet-phy-pair-order = <1>;
&mdio_bus2 {
phy25: ethernet-phy@25 {
reg = <25>;
realtek,smi-address = <9>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
};

20
target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts
View file

@ -8,12 +8,20 @@
model = "Zyxel XGS1210-12 A1 Switch";
};
&phy24 {
realtek,smi-address = <8>;
enet-phy-pair-order = <1>;
&mdio_bus1 {
phy24: ethernet-phy@24 {
reg = <24>;
realtek,smi-address = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
};
&phy25 {
realtek,smi-address = <9>;
enet-phy-pair-order = <1>;
&mdio_bus2 {
phy25: ethernet-phy@25 {
reg = <25>;
realtek,smi-address = <9>;
compatible = "ethernet-phy-ieee802.3-c45";
enet-phy-pair-order = <1>;
};
};

16
target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts
View file

@ -8,10 +8,18 @@
model = "Zyxel XGS1210-12 B1 Switch";
};
&phy24 {
realtek,smi-address = <1>;
&mdio_bus1 {
phy24: ethernet-phy@24 {
reg = <24>;
realtek,smi-address = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&phy25 {
realtek,smi-address = <2>;
&mdio_bus2 {
phy25: ethernet-phy@25 {
reg = <25>;
realtek,smi-address = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};

18
target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
View file

@ -124,24 +124,6 @@
};
};
&mdio_bus1 {
phy24: ethernet-phy@24 {
reg = <24>;
compatible = "ethernet-phy-ieee802.3-c45";
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
};
&mdio_bus2 {
phy25: ethernet-phy@25 {
reg = <25>;
compatible = "ethernet-phy-ieee802.3-c45";
// Disabled because we do not know how to bring up again
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
};
&switch0 {
ethernet-ports {
#address-cells = <1>;