forked from mirror/openwrt
realtek: clk: add rtl9607 clock support
This commit adds support for RTL9607C/RTL8198D clocks to the existing clk-rtl83xx driver. Setting clock rates is not supported due to lack of knowledge on this topic at the moment. Clocks for CPU1, SRAM and SPI can also be calculated but not included in this commit. Since the registers, calculations are widely different to RTL83XX it was decide to have different clk_ops for RTL960X. The code was partly based on naseef's work with some changes to integrate it into the clk-rtl83xx driver. Tested-by: Ahmed Naseef <naseefkm@gmail.com> Signed-off-by: Rustam Adilov <adilov@tutamail.com> Link: https://github.com/openwrt/openwrt/pull/22080 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Rustam Adilov
Robert Marko
parent
10db6fc26e
commit
1af29dbb4f
3 changed files with 127 additions and 5 deletions
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@ -7,13 +7,14 @@ menuconfig COMMON_CLK_REALTEK
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if COMMON_CLK_REALTEK
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config COMMON_CLK_RTL83XX
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bool "Clock driver for Realtek RTL83XX"
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bool "Clock driver for Realtek RTL83XX and RTL960X"
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depends on MACH_REALTEK_RTL
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select SRAM
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help
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This driver adds support for the Realtek RTL83xx series basic clocks.
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This includes chips in the RTL838x series, such as RTL8380, RTL8381,
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RTL832, as well as chips from the RTL839x series, such as RTL8390,
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RT8391, RTL8392, RTL8393 and RTL8396.
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RTL832, chips from the RTL839x series, such as RTL8390, RT8391,
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RTL8392, RTL8393 and RTL8396 as well as chips from the RTL960X
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series, such as RTL9607C, RTL8198D.
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endif
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@ -92,7 +92,8 @@
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#define SOC_RTL838X 0
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#define SOC_RTL839X 1
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#define SOC_COUNT 2
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#define SOC_RTL960X 2
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#define SOC_COUNT 3
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#define MEM_DDR1 1
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#define MEM_DDR2 2
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@ -264,6 +265,8 @@ static const struct rtcl_round_set rtcl_round_set[SOC_COUNT][CLK_COUNT] = {
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RTCL_ROUND_SET(400000000, 850000000, 25000000),
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RTCL_ROUND_SET(100000000, 400000000, 25000000),
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RTCL_ROUND_SET(50000000, 200000000, 50000000)
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}, {
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RTCL_ROUND_SET(500000000, 1200000000, 25000000)
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}
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};
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@ -465,6 +468,91 @@ static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long
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return rrate;
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}
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static unsigned long rtcl_960x_cpu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 ocp_pll_ctrl0, ocp_pll_ctrl3, cmu_gcr;
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u32 cpu_freq_sel0, en_div2_cpu0, cmu_mode, freq_div;
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unsigned long rate;
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ocp_pll_ctrl0 = read_soc(RTL960X_OCP_PLL_CTRL0);
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ocp_pll_ctrl3 = read_soc(RTL960X_OCP_PLL_CTRL3);
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cmu_gcr = read_soc(RTL960X_CMU_GCR);
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cpu_freq_sel0 = RTL960X_OCP_CTRL0_CPU_FREQ_SEL0(ocp_pll_ctrl0);
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en_div2_cpu0 = RTL960X_OCP_CTRL3_EN_DIV2_CPU0(ocp_pll_ctrl3);
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cmu_mode = RTL960X_CMU_GCR_CMU_MODE(cmu_gcr);
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freq_div = RTL960X_CMU_GCR_FREQ_DIV(cmu_gcr);
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rate = ((cpu_freq_sel0 + 2) * 2 * parent_rate) >> en_div2_cpu0;
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if (cmu_mode != 0)
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rate >>= freq_div;
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return rate;
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}
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static unsigned long rtcl_960x_lxb_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 phy_rg5x_pll, lx_freq_sel;
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unsigned long rate;
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phy_rg5x_pll = read_sw(RTL960X_PHY_RG5X_PLL);
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lx_freq_sel = RTL960X_LX_FREQ_SEL(phy_rg5x_pll);
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rate = (40 * parent_rate) / (lx_freq_sel + 5);
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return rate;
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}
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static unsigned long rtcl_960x_mem_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 mem_pll_ctrl2, mem_pll_ctrl3, mem_pll_ctrl5;
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u32 n_code, pdiv, f_code;
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unsigned long rate;
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u64 t;
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mem_pll_ctrl2 = read_soc(RTL960X_MEM_PLL_CTRL2);
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mem_pll_ctrl3 = read_soc(RTL960X_MEM_PLL_CTRL3);
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mem_pll_ctrl5 = read_soc(RTL960X_MEM_PLL_CTRL5);
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pdiv = RTL960X_MEM_CTRL2_PDIV(mem_pll_ctrl2);
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n_code = RTL960X_MEM_CTRL3_N_CODE(mem_pll_ctrl3);
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f_code = RTL960X_MEM_CTRL5_F_CODE(mem_pll_ctrl5);
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rate = (parent_rate * (n_code + 3)) / (2 * (1 << pdiv));
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t = parent_rate;
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t *= f_code;
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t /= 16384;
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rate += t;
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return rate;
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}
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static unsigned long rtcl_960x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
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unsigned long rate;
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if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= SOC_COUNT))
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return 0;
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switch (clk->idx) {
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case CLK_CPU:
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rate = rtcl_960x_cpu_recalc_rate(hw, parent_rate);
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break;
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case CLK_MEM:
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rate = rtcl_960x_mem_recalc_rate(hw, parent_rate);
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break;
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case CLK_LXB:
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rate = rtcl_960x_lxb_recalc_rate(hw, parent_rate);
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break;
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}
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return rate;
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}
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/*
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* Initialization functions to register the CCU and its clocks
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*/
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@ -474,6 +562,10 @@ static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long
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(void *)&rtcl_##SOC##_dram_start) + \
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(void *)PBASE; })
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static const struct clk_ops rtcl_960x_clk_ops = {
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.recalc_rate = rtcl_960x_recalc_rate,
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};
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static const struct clk_ops rtcl_clk_ops = {
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.set_rate = rtcl_set_rate,
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.round_rate = rtcl_round_rate,
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@ -488,6 +580,8 @@ static int rtcl_ccu_create(struct device_node *np)
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soc = SOC_RTL838X;
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else if (of_device_is_compatible(np, "realtek,rtl8390-clock"))
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soc = SOC_RTL839X;
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else if (of_device_is_compatible(np, "realtek,rtl9607-clock"))
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soc = SOC_RTL960X;
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else
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return -ENXIO;
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@ -516,10 +610,14 @@ static int rtcl_register_clkhw(int clk_idx)
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rclk->hw.init = &hw_init;
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hw_init.num_parents = 1;
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hw_init.ops = &rtcl_clk_ops;
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hw_init.parent_data = &parent_data;
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hw_init.name = rtcl_clk_info[clk_idx].name;
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if (rtcl_ccu->soc == SOC_RTL960X)
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hw_init.ops = &rtcl_960x_clk_ops;
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else
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hw_init.ops = &rtcl_clk_ops;
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ret = of_clk_hw_register(rtcl_ccu->np, &rclk->hw);
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if (ret)
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return ret;
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@ -719,6 +817,7 @@ static void __init rtcl_probe_early(struct device_node *np)
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CLK_OF_DECLARE_DRIVER(rtl838x_clk, "realtek,rtl8380-clock", rtcl_probe_early);
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CLK_OF_DECLARE_DRIVER(rtl839x_clk, "realtek,rtl8390-clock", rtcl_probe_early);
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CLK_OF_DECLARE_DRIVER(rtl960x_clk, "realtek,rtl9607-clock", rtcl_probe_early);
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/*
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* Late registration: Finally register as normal platform driver. At this point
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@ -26,6 +26,8 @@
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#define RTL839X_PLL_MEM_CTRL0 (0x0048)
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#define RTL839X_PLL_MEM_CTRL1 (0x004c)
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#define RTL960X_PHY_RG5X_PLL (0x1f054)
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#define RTL_PLL_CTRL0_CMU_SEL_PREDIV(v) (((v) >> 0) & 0x3)
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#define RTL_PLL_CTRL0_CMU_SEL_DIV4(v) (((v) >> 2) & 0x1)
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#define RTL_PLL_CTRL0_CMU_NCODE_IN(v) (((v) >> 4) & 0xff)
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@ -49,6 +51,8 @@
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#define RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(v) (((v) >> 2) & 0x1)
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#define RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(v) (((v) >> 0) & 0x3)
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#define RTL960X_LX_FREQ_SEL(v) ((v) & 0xf)
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/*
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* Core registers (e.g. memory controller)
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*/
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@ -67,6 +71,24 @@
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#define RTL_MC_MCR_DRAMTYPE(v) ((((v) >> 28) & 0xf) + 1)
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#define RTL_MC_DCR_BUSWIDTH(v) (8 << (((v) >> 24) & 0xf))
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#define RTL960X_OCP_PLL_CTRL0 (0x0200)
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#define RTL960X_OCP_PLL_CTRL3 (0x020c)
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#define RTL960X_CMU_GCR (0x0380)
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#define RTL960X_MEM_PLL_CTRL2 (0x023c)
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#define RTL960X_MEM_PLL_CTRL3 (0x0240)
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#define RTL960X_MEM_PLL_CTRL5 (0x0248)
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#define RTL960X_OCP_CTRL0_CPU_FREQ_SEL0(v) (((v) >> 16) & 0x3f)
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#define RTL960X_OCP_CTRL3_EN_DIV2_CPU0(v) (((v) >> 18) & 0x1)
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#define RTL960X_CMU_GCR_CMU_MODE(v) ((v) & 0x3)
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#define RTL960X_CMU_GCR_FREQ_DIV(v) (((v) >> 4) & 0x7)
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#define RTL960X_MEM_CTRL2_PDIV(v) (((v) >> 14) & 0x3)
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#define RTL960X_MEM_CTRL3_N_CODE(v) (((v) >> 24) & 0xff)
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#define RTL960X_MEM_CTRL5_F_CODE(v) ((v) & 0x1fff)
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/*
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* Other stuff
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*/
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