Upstream 2b81db8a7f4475e141a8ffd7cc745ed9f15962df introduced several new
symbols. This commit adds them and also applies alphabetical order via
./scripts/kconfig.pl target/linux/generic/config-6.12
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/22276
Signed-off-by: Robert Marko <robimarko@gmail.com>
Release previously allocated memory and OF node before return.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22276
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93xx devices can no longer find the switch node in the DTS.
Commit 4c92254 ("relocate/retype switch node") refactored the
switch node definition to better align with upstream. Sadly
the redefinition for RTL93xx devices failed.
- RTL83xx: use "switch0: ethernet-switch"
- RTL93xx: use "switch0: switch@1b000000"
Follow up commit 8b969f7 ("drop realtek,smi-address property)
changed the dts lookup sequence for mdio initialization. On
RTL93xx devices it cannot find the switchnode via
of_get_child_by_name(dev->of_node->parent, "ethernet-switch")
Fix the switch node type for RTL93xx
Fixes: 8b969f7 ("drop realtek,smi-address property)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22557
Signed-off-by: Robert Marko <robimarko@gmail.com>
During RX calibration we use a vth_min value of 0 while the SDK always
uses a value of 1 [1]. While we do not know right now which effect this
really has, sync this to the SDK. In worst case we might have an
insufficient calibration result at the moment which usually might be
fine.
[1] 82af3a36b7/sources/rtk-dms1250/src/dal/longan/dal_longan_sds.c (L173)
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
The order within the FGCAL code is not optimal. Right now, there's
output printed even in successful cases (which doesn't really help) and
a value is read although it isn't used if the run succeeds. To fix both,
move that below the success loop exit so it's just printed in
non-success case where the information might be helpful.
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Simplify some register writes being different for even and odd SerDes by
removing if-else and use ternary operator instead. This makes code
shorter and more readable.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Comparing our calibration check with the one in the SDK ([1]), one can
see some discrepancies for which there are no apparent reasons. SGMII
and 1000Base-X are handled equal to XSGMII although they aren't in the
SDK and have different symbol error registers. USXGMII and 10GBase-R are
fine, but other modes are explicitly handled with failure then.
Restructure this by keeping XSGMII alone with its dedicated check (as
the SDK does) and handle all other modes differently. Though the SDK
just skips symbol error check for modes like SGMII, 1000Base-X,
2500Base-X, it was found to be ok to perform a simple check for them
too. Since we have also a default case in the symbol error read
implementation now, we can cover all other modes with default case here
too. As a side-effect, this removes the confusing and probably wrong
failure stating calibration has failed although just the checks were
insufficient.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Our implementation waiting for RX idle signal of a 10G SerDes deviates
from what the SDK does. While we timeout after 100 reads and thus cannot
really control the real time, the SDK times out after 10ms. Adjust that
accordingly by switching the timeout to ktime_* functions with a 10ms
timeout as per the SDK.
While at it, improve the overall style of the function a bit.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the symbol error read implementation to be usable for other modes
too. While we handle other modes as 'not supported', the SDK has a
generic read used in the 'default' case. Do the same so we can have
proper 2500Base-X support here and avoid confusing error messages.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Instead of performing a dedicated register read we can rely on the mode
that is passed via a parameter to the function. The code flow ensures
that this is the same value in this place.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Part of the calibration procedure contains some weird and harebrained
piece of code where a specific register write is guarded by a check for
the SerDes mode, otherwise an error is printed. But right after this
if-else block, the exact same write is applied anyway. Remove this
brain-dead piece of code with something meaningful, i.e. reference code
from the SDK [1]. Over there, more writes are applied and a proper check
is in place.
While at it, add some another comment to the code. While it is
honourable to have code developed by someone quite some time ago that
works, it's discouraged to just have code without any explanation
especially if it differs from the SDK.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Calibration for RTL930x uses multiple iterations for several checks.
While this is fine and needed, it shouldn't be allowed to run forever in
trust that at some point there will always be a "valid" value causing a
loop exit. This has occured a couple of times, causing the driver to
loop forever in case something doesn't run as expected.
To avoid this (and in general as a good practice) limit the affected
loop to a rough estimate of 10 iterations instead of running possibly
forever. The estimate is based on the fact that under normal conditions
it usually takes 1 or 2 to iterations to succeed, more is likely never
to succeed but 10 gives some reasonable headroom.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Cleanup some comments in the code by reducing them to the essential and
putting them behind a line in favor of above. Also simplify some output
prints for the same purpose.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Every devices of mpc85xx was switched to DSA.
Swconfig can be removed.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22161
Signed-off-by: Robert Marko <robimarko@gmail.com>
Convert the P2020RDB DTS to DSA for the VSC7385 switch, add port
labels and fixed-link. Update board network defaults, preinit iface,
and compat version, and include the DSA switch kmod in the image.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22161
Signed-off-by: Robert Marko <robimarko@gmail.com>
A phy node in the dts has two properties:
- reg: the (overall) address of the phy
- realtek,smi-address: the address of the phy on its bus
This notation does not align with upstream. reg should be the address
of the phy on its bus. But where to get the overall address that is
needed for register writes to the hardware?
Luckily the mdio driver and the hardware design sync the ports and
phys (overall) addresses. Thus derive missing data from the dts port
nodes (below ethernet-ports). To realize this
- carve out the port mapping into a separate function to align with
the upstream driver.
- do more sanity checks and catch more inconsistencies
- raise more/better errors via dev_err_probe()
With this commit all dts files must be rewritten as follows:
- if phy has no realtek,smi-address leave it as is
- if phy has realtek,smi-address, write that value into the reg
property and drop realtek,smi-address.
Remark: This commit might bring some confusion about the phyXX and
phy@YY and <reg=YY> naming convention. To be somehow consistent with
the current port/phy identifiers from now on the dts will have:
- phyXX: where XX matches the port number
- phy@YY: where YY is the phy address on the mdio bus
- <reg=YY>: where YY is the phy address on the mdio bus
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The switch node is currently located outside of the switchcore@1b000000
tree. This makes it hard to find when referencing from other nodes in
this tree. Make it a subnode of switchcore and "retype" it to
ethernet-switch like upstream does.
This is not perfectly aligned as upstream just mixes the switchcore and
the ethernet-switch node into one. But this will be future work for
downstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The Zyxel XGS1x10 DTS overzealously tries to avoid redundancies. For
this the phy24/phy25 definitions were split into a common and a device
specific part. Understanding how these phys are defined is therefore
a little bit tricky. Add a little bit of redundancy to make the
definitions easier to read and understand in a single location.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
NN6000v1 Specifications:
SoC: Qualcomm IPQ6000 1.2GHz
RAM: K4B4G1646E-BCMA 512MiB x2 = 1 GiB
Flash: FORESEE 256GB eMMC
ETH: QCA8075 (2x LAN, 1x WAN)
WLAN1: QCN5022 2.4GHz AX 2x2
WLAN2: QCN5052 5GHz AX 2x2
Power: DC 12V
Button: Reset, Wps
USB: 1x 3.0
NN6000v2 Specifications:
SoC: Qualcomm IPQ6000 1.2GHz
RAM: MT41K512M16VRN-107 IT:P 1GiB x2 = 2 GiB
Flash: FORESEE 256GB eMMC
ETH: QCA8075 (4x LAN, 1x WAN)
WLAN1: QCN5022 2.4GHz AX 2x2
WLAN2: QCN5052 5GHz AX 2x2
Power: DC 12V
Button: Reset, Wps
USB: 1x 3.0
Install via UART:
1. Download the initramfs image, rename it to
initramfs.itb, host it with the tftp server.
2. Interrupt U-Boot and run these commands:
tftpboot initramfs.itb
bootm
3. After openwrt boots up, use scp or luci web
to upload sysupgrade.bin to upgrade.
Install via Uboot WebUI:
- Only work when you flash a custom uboot with webui
- Push the reset button for 5 seconds, then use broswer to
access http://192.168.1.1/, then upload factory.bin.
Signed-off-by: Fire Chen <firedevel@icloud.com>
Link: https://github.com/openwrt/openwrt/pull/21787
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
NVMEM on MMC was added in dts but the corresponding option was not added
to the config.
Fixes: ee5999c ("treewide: linksys: use nvmem MAC for hw_mac_addr")
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22539
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The issue described in the patch has been fixed by commit
604355e8c4 ("kernel: fix fraglist GRO on linux 6.12")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22525
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The initial mt76x8 kernel config file was inherited from mt7620
sub-target. However, This SoC series doesn't support any external
PHY. We can disable CONFIG_ICPLUS_PHY symbol to reduce kernel size.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22519
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport more upstream patch to include all the fixes pushed upstream and
add all the preliminary patch for multi-serdes support.
While at it also move 2 patch in the 6xx numbering to the 000-1xx backport
numbering to keep things tidy.
All the affected patch manually and automatically refreshed.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
[ add comment, renumber patch, add more patch, fix PCS patch ]
Link: https://github.com/openwrt/openwrt/pull/22479
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport new field_prep()/get() particularly useful to handle case where a
bitmask is not const and FIELD_PREP can't be used. This permit to replace
manual shift with these macro. (also needed to permit backport of some
patch without modification)
Backport reworked patch that drop the local field_prep()/get() macro in
favor of the global one.
Link: https://github.com/openwrt/openwrt/pull/22479
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Renumber ASoC and PCS patch to 2xx and 3xx numbering to leave space for
more backport patch in the 000-1xx numbering.
Link: https://github.com/openwrt/openwrt/pull/22479
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
These targets seems to be left over, so changed as other targets
covered by commit d35d92a .
Signed-off-by: Edward Chow <equu@openmail.cc>
Link: https://github.com/openwrt/openwrt/pull/22510
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for RTL9607C/RTL8198D clocks to the existing
clk-rtl83xx driver. Setting clock rates is not supported due to
lack of knowledge on this topic at the moment. Clocks for CPU1, SRAM
and SPI can also be calculated but not included in this commit.
Since the registers, calculations are widely different to RTL83XX it
was decide to have different clk_ops for RTL960X.
The code was partly based on naseef's work with some changes to
integrate it into the clk-rtl83xx driver.
Tested-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22080
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently, devices having two cpu ports to the switch managed by swconfig,
especally those with qca955x, line tplink archer c7 v2 and linksys ea4500 v3,
use vlan on different cpu port to separate networks by default. (e.g. eth1.1
for lan, eth0.2 for wan)
However, untagging to these vlans cpu ports, and limiting vlans in the switch
on these devices could effectively offload the expense to process vlan tag from
cpu to the switch, and increase the throughput of lan <-> wan ipoe routing.
Tested on my tplink tl-wdr4900 v2, where ucidef_add_switch "switch0"
"0u@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6u@eth0" "1:wan" finally generates
on /etc/config/network:
config device
option name 'br-lan'
option type 'bridge'
list ports 'eth1'
config interface 'lan'
option device 'br-lan'
option proto 'static'
list ipaddr '192.168.1.1/24'
option ip6assign '60'
config interface 'wan'
option device 'eth0'
option proto 'dhcp'
config interface 'wan6'
option device 'eth0'
option proto 'dhcpv6'
config switch
option name 'switch0'
option reset '1'
option enable_vlan '1'
config switch_vlan
option device 'switch0'
option vlan '1'
option ports '2 3 4 5 0'
config switch_vlan
option device 'switch0'
option vlan '2'
option ports '1 6'
and the throughput of lan <-> wan ipoe routing with software flow offload
increases from around
[850 Mbps](https://openwrt.org/toh/tp-link/archer-c5-c7-wdr7500#nat_performance)
to 900 Mbps.
Signed-off-by: Edward Chow <equu@openmail.cc>
Link: https://github.com/openwrt/openwrt/pull/19444
Signed-off-by: Robert Marko <robimarko@gmail.com>
These devices use the binding + eeprom-swap. Turns out the reason swap
is needed is because the binding wrongly swaps the data on big endian
hosts. NVMEM doesn't do this and thus just works.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22207
Signed-off-by: Robert Marko <robimarko@gmail.com>
A size of 600 is incomplete in that calibration data is not included,
resulting in low TX power.
Fixes: 64dae105 ("ramips: mt76x8: add support for Yuncore CPE200")
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22459
Signed-off-by: Robert Marko <robimarko@gmail.com>
The dtsi used handles a bunch of non-DBDC platforms where the
assignments are correct. The 3040-a1 is different as there are 3 instead
of 2 wifi interfaces and WAN needs to be incremented by 1.
Remove userspace wifi assignmwent which was needed before per band nvmem
was supported.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21977
Signed-off-by: Robert Marko <robimarko@gmail.com>
While rebasing, a typo was made where the ';;' terminator was omitted in
the 02_network script. Add it to restore script functionality.
Fixes: e210d994fa ("airoha: an7581: add Nokia Valyrian support")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
- Update network port names based on the shell
- Fix boot log errors:
OF: /soc/pcie@11280000/pcie@0,0: Missing device_type
- Match vendor firmware Ethernet and wireless MAC addresses
LAN MAC 50:xx:xx:xx:xx:60
WAN MAC 50:xx:xx:xx:xx:61
2G MAC 50:xx:xx:xx:xx:63
5G MAC 50:xx:xx:xx:xx:65
Fixes: 7d79346581 ("mediatek: filogic: add support for Tenda BE12 Pro")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/22060
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Add support for Nokia Valyrian based on Airoha AN7581 SoC.
Device specification
--------------------
SoC Type: Airoha AN7581
RAM: 2x DDR4 Nanya NT5AD256M16E4-JR (1GB)
Flash: eMMC Macronix MX52LM08A11XVW (1GB)
Ethernet: 3x gigabit via AN7581, 1x 10g via AS21x1x, 1x SFP cage
Wi-Fi: MT7996 - BE19000
LEDs: 11 LED via 2x 74HC595 shift register
Button: Reset, WPS, WiFi
USB ports: 1x 2.0
Miscellaneous: 1x Power Monitor via RTQ6059, 2x FXS port
Device is unfused and is originally flashed with Airoha SDK bootloader
that require signed images.
Bootloader is username/password protected and use the leaked auth combo
that can be found online.
From the bootloadet instruction on how to flash custom bootloader are:
1. mmc erase 0 0x800
2. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-preloader.bin
3. mmc write $loadaddr 0x4 0xfc
4. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-bl31-uboot.fip
5. mmc write $loadaddr 0x100 0x700
It's also possible to use the Emergency Recovery procedure:
From powered OFF device:
1. Keep the reset button pressed (middle button)
2. Power on the device
3. Notice the "Press x" prompt
4. Press x
5. Notice the "C" char waiting for XMODEM load
6. Load the preloader binary with XMODEM protocol
7. Notice the "Press x to load BL31 + U-Boot FIP"
8. Press x
9. Notice the "C" char waiting for XMODEM load
10. Load the fip binary with XMODEM protocol
11. You are now in U-Boot loaded from serial
12. Follow normal procedure to flash bootloader
Due to BOOTROM limitation. the device can't have a standard GPT table
implementation. Because of this fixed-partitions are used to handle this.
U-Boot still doesn't have support for this (it's planned) and currently to flash
and load and image it's needed to write and read from static address in eMMC.
The GPT partition table follow Prpl guidelines with dual partition table with
kernel and rootfs split.
The address for kernel is 0xb00000 and the address for rootfs is 0x1b00000.
Link: https://github.com/openwrt/openwrt/pull/21761
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Set nand flash for KN-1910
Sysupgrade or any other method i tried (asu, owut) not working without it. Tested with a local build.
Signed-off-by: Esat Yiğithan GÖKTOPRAK <eygoktoprak@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22311
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The bootcount init script is missing the executable bit (644 instead of 755),
causing the script to not be executable:
/etc/preinit: line 44: /etc/init.d/bootcount: Permission denied
Fixes: c3b8108a2b ("ramips: Add support for Xiaomi MiWiFi 3A")
Signed-off-by: Oliver Sedlbauer <os@dev.tdt.de>
Link: https://github.com/openwrt/openwrt/pull/22446
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MIPS code assigns the clock node based on the device tree node name.
This name was renamed with kernel 6.12.58 and v6.6.117. Adapt our out of
tree device tree files to this rename to fix loading the STP GPIO
driver.
Without this fix the driver fails like this:
```
[ 0.320000] gpio-stp-xway 1e100bb0.stp: Failed to get clock
[ 0.330000] gpio-stp-xway 1e100bb0.stp: probe with driver gpio-stp-xway failed with error -2
```
Link: https://git.kernel.org/linus/b0d04fe6a633ada2c7bc1b5ddd011cbd85961868
Fixes: https://github.com/openwrt/openwrt/issues/21697
Co-Authored-By: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22444
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Certain targets for an7581 and an7583 referred to kmod-pwm-airoha;
however in the target modules makefile the module is referred to
as kmod-pwm-an7581, causing buildbot to fail.
Change the name of kmod-pwm-an7581 to kmod-pwm-airoha to resolve this.
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/22445
Signed-off-by: Robert Marko <robimarko@gmail.com>
W1700K fan script is missing the #!/bin/sh /etc/rc.common shebang and
requires execution bits set. Also, set the fallback to hwmon 3 instead
of 5, since the new RTL PHY driver was not merged.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22391
Signed-off-by: Robert Marko <robimarko@gmail.com>
Note that for working G.hn support some packages need to be extracted from the Devolo firmware.
Signed-off-by: Julius Schwartzenberg <julius.schwartzenberg@eclipso.eu>
Link: https://github.com/openwrt/openwrt/pull/22123
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Developers no longer maintain this driver. And it has been replaced
by the new upstream implementation. It's time to say goodbye.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is the generic PWM framework driver for Mediatek SoC. Now
this module is ready for MT7628.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The upstream MediaTek PWM driver requires these clock sources to
work properly.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22214
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When running `make kernel_menuconfig`, CPU_BIG_ENDIAN is selected by
default, resulting in a non-bootable image. Add CPU_LITTLE_ENDIAN to
avoid that.
Signed-off-by: Qingfang Deng <dqfext@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22282
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The device dts files were moved to the dedicated directory in commit
a66e30631c ("qualcommax: move Device DTS to dedicated DTS directory"),
which resulted in a merge conflict.
Fixes: d755c49f7a ("qualcommax: ipq60xx: rename TP-Link EAP623-Outdoor HD v1 compatible")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22433
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for RTL9607C / RTL8198D thermal controller.
Based on the Realtek SDK code.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22081
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL8226 PHYs in Zyxel XGS1010-10 and XGS1210-10 rev A1 have swapped
MDI lanes. Specify this in the device tree, so the driver can configure
it. With this change, the PHYs no longer require initialization by the
bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
