York Sun ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 ... Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-10-22 14:31:32 -05:00
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74xx_7xx	unify version_string	2011-07-28 17:22:53 +02:00
mpc5xx	serial: Use default_serial_puts() in drivers	2012-10-17 07:55:50 -07:00
mpc5xxx	usb: lowlevel interface change to support multiple controllers	2012-10-15 11:54:00 -07:00
mpc8xx	serial: mpc8xx: Move serial registration from serial_initialize()	2012-10-15 11:53:49 -07:00
mpc8xxx	powerpc/mpc8xxx: Fix DDR SPD failed message	2012-10-22 14:31:31 -05:00
mpc83xx	MPC83xx, MPC85xx: compile stub cache function	2012-07-21 23:37:48 +02:00
mpc85xx	powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1	2012-10-22 14:31:32 -05:00
mpc86xx	powerpc/mpc85xx: software workaround for DDR erratum A-004468	2012-10-22 14:31:28 -05:00
mpc512x	serial: Remove CONFIG_SERIAL_MULTI from serial drivers	2012-10-15 11:53:58 -07:00
mpc824x	mpc82xx: Remove BMW board port	2012-10-17 07:55:50 -07:00
mpc8220	serial: Use default_serial_puts() in drivers	2012-10-17 07:55:50 -07:00
mpc8260	serial: Use default_serial_puts() in drivers	2012-10-17 07:55:50 -07:00
ppc4xx	usb: lowlevel interface change to support multiple controllers	2012-10-15 11:54:00 -07:00