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York Sun ffd06e0231 powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:32 -05:00
..
cpu powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 2012-10-22 14:31:32 -05:00
include/asm powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 2012-10-22 14:31:32 -05:00
lib powerpc/mpc85xx: software workaround for DDR erratum A-004468 2012-10-22 14:31:28 -05:00
config.mk Handle most LDSCRIPT setting centrally 2011-04-30 00:59:47 +02:00