Aneesh V f1f2c3ca9f armv7: omap3: leave outer cache enabled ... Mainline kernel for OMAP3 doesn't enable L2 cache It expects L2$ to be enabled by ROM-code/bootloader. Leaving L2$ enabled can be troublesome in cases where the L2 cache is not under CP15 control, such as in Cortex-A9. This problem is explained in detail in the commit dc7100f408 However, this problem doesn't apply to Cortex-A8 because L2$ in Cortex-A8 is under CP15 control and hence the generic armv7 maintenance opertions work for it. As such we can make an exception for OMAP3 and leave the L2$ enabled when we jump to kernel. This is done by removing the strongly-linked implementation of v7_outer_cache_disable() and allowing it to fall back to the weakly linked implementation that doesn't do anything. Signed-off-by: Aneesh V <aneesh@ti.com>		2012-02-27 21:19:25 +01:00
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arm720t	Reduce build times	2011-11-03 20:44:58 +01:00
arm920t	add print_cpuinfo to s3c24x0	2011-12-19 17:52:44 +01:00
arm925t	Reduce build times	2011-11-03 20:44:58 +01:00
arm926ejs	dm6467Tevm: Use a common configuration file for davinci_dm6467evm and davinci_dm6467Tevm	2012-02-27 21:19:24 +01:00
arm946es	Reduce build times	2011-11-03 20:44:58 +01:00
arm1136	mx35: generic: Let get_reset_cause be defined only when CONFIG_DISPLAY_CPUINFO is selected	2012-02-27 21:19:24 +01:00
arm1176	Reduce build times	2011-11-03 20:44:58 +01:00
arm_intcm	Reduce build times	2011-11-03 20:44:58 +01:00
armv7	armv7: omap3: leave outer cache enabled	2012-02-27 21:19:25 +01:00
ixp	Reduce build times	2011-11-03 20:44:58 +01:00
lh7a40x	Reduce build times	2011-11-03 20:44:58 +01:00
pxa	pxa: activate the first usb host port on pxa27x by default	2011-12-11 14:41:05 +01:00
s3c44b0	Reduce build times	2011-11-03 20:44:58 +01:00
sa1100	Reduce build times	2011-11-03 20:44:58 +01:00