Aneesh V f1f2c3ca9f armv7: omap3: leave outer cache enabled ... Mainline kernel for OMAP3 doesn't enable L2 cache It expects L2$ to be enabled by ROM-code/bootloader. Leaving L2$ enabled can be troublesome in cases where the L2 cache is not under CP15 control, such as in Cortex-A9. This problem is explained in detail in the commit dc7100f408 However, this problem doesn't apply to Cortex-A8 because L2$ in Cortex-A8 is under CP15 control and hence the generic armv7 maintenance opertions work for it. As such we can make an exception for OMAP3 and leave the L2$ enabled when we jump to kernel. This is done by removing the strongly-linked implementation of v7_outer_cache_disable() and allowing it to fall back to the weakly linked implementation that doesn't do anything. Signed-off-by: Aneesh V <aneesh@ti.com>		2012-02-27 21:19:25 +01:00
..
cpu	armv7: omap3: leave outer cache enabled	2012-02-27 21:19:25 +01:00
include/asm	tt01: add video support	2012-02-27 21:19:25 +01:00
lib	davinci: add support for printing clock frequency	2012-02-12 10:11:32 +01:00
config.mk	Reduce build times	2011-11-03 20:44:58 +01:00