mirror of
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eed8fc7b0d
Change-Id: I2893089a3b0ca91ea22d49417934f126398a6a58 Signed-off-by: anusha <anusharao@codeaurora.org>
773 lines
25 KiB
C
773 lines
25 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2020 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QPIC_NAND_H
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#define __QPIC_NAND_H
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#if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI) \
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|| defined(CONFIG_IPQ6018) || defined(CONFIG_IPQ5018) \
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|| defined(CONFIG_IPQ9574)
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#define QPIC_EBI2ND_BASE (0x079b0000)
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#else
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#error "QPIC NAND not supported"
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#endif
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#define QPIC_BAM_CTRL_BASE (0x07984000)
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#define NAND_REG(off) (QPIC_EBI2ND_BASE + (off))
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#define NAND_FLASH_CMD NAND_REG(0x0000)
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#define NAND_ADDR0 NAND_REG(0x0004)
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#define NAND_ADDR1 NAND_REG(0x0008)
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#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
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#define NAND_EXEC_CMD NAND_REG(0x0010)
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#define NAND_FLASH_STATUS NAND_REG(0x0014)
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#define NAND_BUFFER_STATUS NAND_REG(0x0018)
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#define NAND_DEV0_CFG0 NAND_REG(0x0020)
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#define NAND_DEV0_CFG1 NAND_REG(0x0024)
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#define NAND_DEV0_ECC_CFG NAND_REG(0x0028)
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#define NAND_DEV1_CFG0 NAND_REG(0x0030)
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#define NAND_DEV1_CFG1 NAND_REG(0x0034)
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#define NAND_SFLASHC_CMD NAND_REG(0x0038)
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#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
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#define NAND_READ_ID NAND_REG(0x0040)
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#define NAND_READ_STATUS NAND_REG(0x0044)
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#define NAND_CONFIG_DATA NAND_REG(0x0050)
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#define NAND_CONFIG NAND_REG(0x0054)
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#define NAND_CONFIG_MODE NAND_REG(0x0058)
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#define NAND_CONFIG_STATUS NAND_REG(0x0060)
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#define NAND_MACRO1_REG NAND_REG(0x0064)
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#define NAND_XFR_STEP1 NAND_REG(0x0070)
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#define NAND_XFR_STEP2 NAND_REG(0x0074)
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#define NAND_XFR_STEP3 NAND_REG(0x0078)
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#define NAND_XFR_STEP4 NAND_REG(0x007C)
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#define NAND_XFR_STEP5 NAND_REG(0x0080)
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#define NAND_XFR_STEP6 NAND_REG(0x0084)
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#define NAND_XFR_STEP7 NAND_REG(0x0088)
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#define NAND_GENP_REG0 NAND_REG(0x0090)
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#define NAND_GENP_REG1 NAND_REG(0x0094)
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#define NAND_GENP_REG2 NAND_REG(0x0098)
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#define NAND_GENP_REG3 NAND_REG(0x009C)
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#define NAND_SFLASHC_STATUS NAND_REG(0x001C)
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#define NAND_DEV_CMD0 NAND_REG(0x00A0)
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#define NAND_DEV_CMD1_V1_4_20 NAND_REG(0x00A4)
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#define NAND_DEV_CMD2 NAND_REG(0x00A8)
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#define NAND_DEV_CMD_VLD_V1_4_20 NAND_REG(0x00AC)
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#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
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#define NAND_ADDR2 NAND_REG(0x00C0)
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#define NAND_ADDR3 NAND_REG(0x00C4)
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#define NAND_ADDR4 NAND_REG(0x00C8)
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#define NAND_ADDR5 NAND_REG(0x00CC)
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#define NAND_DEV_CMD3 NAND_REG(0x00D0)
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#define NAND_DEV_CMD4 NAND_REG(0x00D4)
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#define NAND_DEV_CMD5 NAND_REG(0x00D8)
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#define NAND_DEV_CMD6 NAND_REG(0x00DC)
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#define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0)
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#define NAND_ADDR6 NAND_REG(0x00E4)
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#define NAND_ERASED_CW_DETECT_CFG NAND_REG(0x00E8)
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#define NAND_ERASED_CW_DETECT_STATUS NAND_REG(0x00EC)
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#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
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#define NAND_HW_INFO NAND_REG(0x00FC)
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#define NAND_FLASH_BUFFER NAND_REG(0x0100)
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#define NAND_MULTI_PAGE_CMD NAND_REG(0x0F60)
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#define NAND_FLASH_FEATURES NAND_REG(0x0F64)
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#define QPIC_NAND_CTRL NAND_REG(0x0F00)
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#define QPIC_NAND_DEBUG NAND_REG(0x0F0C)
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/* Additional Register set for Serial NAND */
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#define NAND_AUTO_STATUS_EN NAND_REG(0x002C)
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#define NAND_VERSION NAND_REG(0x4F08)
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#define SPI_NAND_DEV_CMD0 NAND_REG(0x70A0)
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#define SPI_NAND_DEV_CMD1 NAND_REG(0x70A4)
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#define SPI_NAND_DEV_CMD2 NAND_REG(0x70A8)
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#define SPI_NAND_DEV_CMD3 NAND_REG(0x70D0)
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#define NAND_FLASH_DEV_CMD_VLD NAND_REG(0x70AC)
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#define SPI_NAND_DEV_CMD7 NAND_REG(0x70B0)
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#define SPI_NAND_DEV_CMD8 NAND_REG(0x70B4)
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#define SPI_NAND_DEV_CMD9 NAND_REG(0x70B8)
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#define NAND_FLASH_SPI_CFG NAND_REG(0x70C0)
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#define NAND_SPI_NUM_ADDR_CYCLES NAND_REG(0x70C4)
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#define NAND_SPI_BUSY_CHECK_WAIT_CNT NAND_REG(0x70C8)
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#define NAND_QSPI_MSTR_CONFIG NAND_REG(0x7f60)
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/* Register mask & shift value used in SPI transfer mode */
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#define SPI_TRANSFER_MODE_1X 0x1
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#define SPI_TRANSFER_MODE_4X 0x3
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/* These value as per HPG , these value as per 2K device*/
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#define SPI_NAND_DEVn_CFG0 0x1A5408D0
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#define SPI_NAND_DEVn_CFG1 0x08287440
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#define SPI_NAND_DEVn_CFG1_RESET 0x087476B1
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/* value for below register according to HPG : 0x42040702 for reset
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* and 0x42040700 for reset disable
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*/
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#define SPI_NAND_DEVn_ECC_CFG 0x42040702
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#define SPI_NAND_DEVn_ECC_CFG_RST_DIS 0x42040700
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#define FLASH_DEV_CMD_VLD 0x0000000D
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/* These Value as per HPG */
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#define NAND_FLASH_DEV_CMD0_VAL 0x1080D8D8
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#define NAND_FLASH_DEV_CMD1_VAL 0xF00F3000
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#define NAND_FLASH_DEV_CMD2_VAL 0xF0FF709F
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#define NAND_FLASH_DEV_CMD3_VAL 0x3F310015
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/* For Micron NAND_FLASH_DEV_CMD3_VAL value should
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* be 0x3F300015
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*/
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#define NAND_FLASH_DEV_CMD7_VAL 0x04061F0F
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#define NAND_FLASH_DEV_CMD7_WE 0x60000
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#define NAND_FLASH_DEV_CMD7_WD 0x40000000
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#define NAND_FLASH_DEV_CMD7_SET_FTR 0x1F00
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#define NAND_FLASH_DEV_CMD7_GET_FTR 0x0F
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#define SPI_BUSY_CHECK_WAIT_CNT 0x00000010
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#define SPI_CFG_VAL 0x1924C00D
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#define SPI_LOAD_CLK_CNTR_INIT_EN (1 << 28)
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#define SPI_NUM_ADDR_CYCLES 0x000DA4DB
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#define NAND_FLASH_SET_FEATURE_MASK 0xB800000E
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#define NAND_FLASH_GET_FEATURE_MASK 0x3800000E
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#define QPIC_HARDWARE_VERSION_2_0 0x20000000
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#define NAND_FLASH_STATUS_MASK 0xC
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#define QPIC_SERIAL_ERROR 517
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#define QPIC_SPI_SET_FEATURE (1 << 31)
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#define QPIC_SPI_GET_FEATURE ~(1 << 31)
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#define QPIC_SPI_WP_SET (1 << 28)
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#define QPIC_SPI_HOLD_SET (1 << 27)
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#define QPIC_SPI_TRANSFER_MODE_X1 (1 << 29)
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#define QPIC_SPI_TRANSFER_MODE_X4 (3 << 29)
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#define QPIC_SPI_BOOST_MODE (1 << 11)
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#define QPIC_SPI_NAND_CTRL_VAL 0x341
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#define QPIC_PAGE_SCOPE_CMD_EN (1 << 23)
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#define QPIC_MULTIPAGE_CMD_EN (1 << 22)
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#define QPIC_LAST_PAGE_MASK (1 << 5)
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/* For all status
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* #define QPIC_SPI_NAND_AUTO_STATUS_VAL 0x003F003F
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*/
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#define QPIC_SPI_NAND_AUTO_STATUS_VAL 0x000B000B
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#define QPIC_SPI_MAX_CODE_WORD_2K_PAGE 0x4
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#define QPIC_SPI_MAX_STATUS_REG 12
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#define QPIC_AUTO_STATUS_BUFFER_SIZE (QPIC_SPI_MAX_CODE_WORD_2K_PAGE * \
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QPIC_SPI_MAX_STATUS_REG)
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#define QPIC_NAND_FLASH_CMD_WE_VAL 0XB800000F
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#define QPIC_NAND_FLASH_CMD_WD_VAL 0x3800000F
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#define WR_EN 0x1
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#define WR_DIS 0x0
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#define PAGE_2KiB_STATUS_BUF_SIZE 48
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#define PAGE_4KiB_STATUS_BUF_SIZE 96
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#define PAGE_8KiB_STATUS_BUF_SIZE 192
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#define PAGE_2KiB 2048
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#define PAGE_4KiB 4096
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#define PAGE_8KiB 8192
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#define MAX_MULTI_PAGE 64
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#define GET_STATUS_BUFF_PARSE_SIZE_PER_PAGE(page_size, parse_size) ({ \
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switch(page_size) { \
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case PAGE_2KiB: \
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parse_size = PAGE_2KiB_STATUS_BUF_SIZE; \
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break; \
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case PAGE_4KiB: \
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parse_size = PAGE_4KiB_STATUS_BUF_SIZE; \
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break; \
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case PAGE_8KiB: \
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parse_size = PAGE_8KiB_STATUS_BUF_SIZE; \
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break; \
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default: \
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break; \
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} \
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})
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#define GET_STATUS_BUFF_ALLOC_SIZE(page_size, status_buf_size) ({ \
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switch(page_size) { \
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case PAGE_2KiB: \
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status_buf_size = PAGE_2KiB_STATUS_BUF_SIZE * \
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MAX_MULTI_PAGE; \
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break; \
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case PAGE_4KiB: \
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status_buf_size = PAGE_4KiB_STATUS_BUF_SIZE * \
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MAX_MULTI_PAGE; \
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break; \
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case PAGE_8KiB: \
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status_buf_size = PAGE_8KiB_STATUS_BUF_SIZE * \
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MAX_MULTI_PAGE; \
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break; \
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default: \
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break; \
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} \
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})
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/* According to GigaDevice data sheet Block Protection Register is:
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* ____________________________________________
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* | | | | | | | | |
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* |BRWD |RSVD| BP2| BP1| BP0| INV | CMP |RSVD |
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* | | | | | | | | |
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* |______|____|____|____|____|_____|_____|_____|
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*
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* NOTE: RSVD = Reserved.
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*
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* After power-up the device is in "locked" state i.e feature bits
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* BP0, BP1, BP2 are set to 1. ENV, CMP, BRWD are set to 0.
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* When BRWD is set to 1 and WP# is LOW i.e 0, none of the writable
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* protection feature bits can be set.
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* When an ERASE command is issued to a locked block, the erase failure,
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* 04H, is returned.
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*
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* With CMP = X, INV = X, BP2 = 0, BP1 = 0, BP0 = 0 : There will be no
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* block protection functionality.
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*
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* When WP# is not LOW, user can issue bellows commands to alter the
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* protection.
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*
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* Issue SET FEATURES register write (1FH)
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* Issue the feature bit address (A0h)
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*/
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#define FLASH_SPI_NAND_BLK_PROCT_ADDR 0xA0
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#define FLASH_SPI_NAND_BLK_PROCT_DISABLE 0x00
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#define FLASH_SPI_NAND_BLK_PROCT_ENABLE 0x78
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/* According to GigaDevice data sheet Feature Register is:
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* _________________________________________________
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* | | | | | | | | |
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* |OTP-PRT|OTP_EN| RSVD|ECC-EN|RSVD|RSVD |RSVD |QE |
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* | | | | | | | | |
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* |_______|______|_____|______|____|_____|_____|____|
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*
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*
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* NOTE : When a feature is set, it remains active until the
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* device is power cycled or the feature is written to.once
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* the device is set, it remains set, even if a RESET (FFH)
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* command is issued.
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*
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* OTP-PRT = X , OTP_EN = 0 : Normal Operation
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* OTP-PRT = 0, OTP_EN = 1 : Access OTP region, read and program data.
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*
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* ECC-EN : ECC is enabled after device power up, so the default
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* READ and PROGRAM commands operate with internal ECC in the “active”
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* state. To enable/disable ECC, perform the following command sequence:
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*
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* 1) Issue the SET FEATURES command (1FH).
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* 2) Set the feature bit ECC_EN as you want:
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* a) To enable ECC, Set ECC_EN to 1.
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* b) To disable ECC, Clear ECC_EN to 0.
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*
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* NOTE: For this device GD5F1GQ4xExxG
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* --> Internal ECC Off (ECC_EN=0):
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* 2048-Byte+128-Byte Full Access.
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*
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* --> Internal ECC On (ECC_EN=1, default):
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* Program: 2048-Byte+64-Byte.
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* Read: 2048-Byte+128-Byte.
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*
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* QE : If QE is enabled, the quad IO operations can be executed.
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*
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*/
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#define FLASH_SPI_NAND_FR_ADDR 0xB0
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#define FLASH_SPI_NAND_FR_ECC_ENABLE (1 << 4)
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#define FLASH_SPI_NAND_FR_BUFF_ENABLE (1 << 3)
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#define FLASH_SPI_NAND_FR_QUAD_ENABLE 0x1
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/* According to GigaDevice data sheet Status Register(0xC0) is:
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* _________________________________________________
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* | | | | | | | | |
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* |RSVD |RSVD |ECCS1|ECCS0|P-FAIL|E-FAIL|WEL |OIP |
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* | | | | | | | | |
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* |______|______|_____|_____|_____ |______|____|____|
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*
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*
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* NOTE: RSVD = Reserved.
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*
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* P-FAIL : This bit indicates that a program failure has occurred
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* (P_FAIL set to 1). It will also be set if the user attempts to
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* program an invalid address or a protected region, including
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* the OTP area.
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*
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* E-FAIL : This bit indicates that an erase failure has occurred
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* (E_FAIL set to 1). It will also be set if the user attempts to
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* erase a locked region.
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*
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* WEL : This bit indicates the current status of the write enable
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* latch (WEL) and must be set (WEL = 1), prior to issuing a
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* PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the
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* WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing
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* the WRITE DISABLE command.
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*
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* OIP : This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ,
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* BLOCK ERASE, or RESET command is executing, indicating the device
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* is busy. When the bit is 0, the interface is in the ready state.
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*
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* ECC Status : ECCS and ECCSE are set to 00b either following a RESET,
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* or at the beginning of the READ.ECCS and ECCSE are invalid if internal
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* ECC is disabled (via a SET FEATURES command to reset ECC_EN to 0).
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*
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* NOTE: After power-on RESET, ECC status is set to reflect the contents
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* of block 0, page 0.
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*/
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#define FLASH_SPI_NAND_SR_ADDR 0xC0
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#define FLASH_SPI_NAND_SR_DATA 0x00
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/* According to GigaDevice data sheet Feature Register(0xD0) is:
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* _________________________________________________
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* | | | | | | | | |
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* |RSVD |DS-S1|DS-S0|RSVD |RSVD |RSVD |RSVD |RSVD|
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* | | | | | | | | |
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* |______|_____|_____|_____|______|______|_____|____|
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*
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* DS-S1 = 0 , DS-S0 = 0 : Drive strength is 50%
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* DS-S1 = 0 , DS-S0 = 1 : Drive strength is 25%
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* DS-S1 = 1 , DS-S0 = 0 : Drive strength is 75%
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* DS-S1 = 1 , DS-S0 = 1 : Drive strength is 100%
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*
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* 00 is the default data byte value for Output Driver Register after power-up
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*/
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#define FLASH_SPI_NAND_FR_DS_ADDR 0xD0
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#define FLASH_SPI_NAND_FR_DS_DATA 0x00
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/* NANDc registers used during BAM transfer */
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#define NAND_READ_LOCATION_n(n) (NAND_REG(0xF20) + 4 * (n))
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#define NAND_READ_LOCATION_LAST_CW_n(n) (NAND_REG(0xF40) + 4 * (n))
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#define NAND_RD_LOC_LAST_BIT(x) ((x) << 31)
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#define NAND_RD_LOC_SIZE(x) ((x) << 16)
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#define NAND_RD_LOC_OFFSET(x) ((x) << 0)
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#define NAND_DEV_CMD_VLD_V1_5_20 NAND_REG(0x70AC)
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#define NAND_DEV_CMD1_V1_5_20 NAND_REG(0x70A4)
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#define NAND_XFR_STEPS_V1_5_20 NAND_REG(0x7070)
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/* Shift Values */
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#define NAND_DEV0_CFG1_WIDE_BUS_SHIFT 1
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#define NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT 4
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#define NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT 6
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#define NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT 9
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#define NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT 27
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#define NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT 23
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#define NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT 2
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#define NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT 5
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#define NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT 6
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#define NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT 16
|
|
#define NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT 17
|
|
#define NAND_DEV0_ECC_DISABLE_SHIFT 0
|
|
#define NAND_DEV0_ECC_SW_RESET_SHIFT 1
|
|
#define NAND_DEV0_ECC_MODE_SHIFT 4
|
|
#define NAND_DEV0_ECC_DISABLE_SHIFT 0
|
|
#define NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT 8
|
|
#define NAND_DEV0_ECC_NUM_DATA_BYTES 16
|
|
#define NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT 30
|
|
|
|
#define NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED 7
|
|
#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED 6
|
|
#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED 4
|
|
#define NAND_CW_ERASED (BIT(NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED) | \
|
|
BIT(NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED))
|
|
|
|
#define NAND_ERASED_CW_DETECT_CFG_RESET_CTRL 1
|
|
#define NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL 0
|
|
#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK (1 << 1)
|
|
#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_NO_MASK (0 << 1)
|
|
|
|
/* device commands */
|
|
#define NAND_CMD_SOFT_RESET 0x01
|
|
#define NAND_CMD_PAGE_READ 0x32
|
|
#define NAND_CMD_PAGE_READ_ECC 0x33
|
|
#define NAND_CMD_PAGE_READ_ALL 0x34
|
|
#define NAND_CMD_SEQ_PAGE_READ 0x15
|
|
#define NAND_CMD_PRG_PAGE 0x36
|
|
#define NAND_CMD_PRG_PAGE_ECC 0x37
|
|
#define NAND_CMD_PRG_PAGE_ALL 0x39
|
|
#define NAND_CMD_BLOCK_ERASE 0x3A
|
|
#define NAND_CMD_FETCH_ID 0x0B
|
|
#define NAND_CMD_RESET_DEVICE 0x0D
|
|
#define NAND_CMD_SET_FEATURE 0x1F
|
|
#define NAND_CMD_GET_FEATURE 0x0F
|
|
#define NAND_CMD_ACC_FEATURE 0x0E
|
|
/* Serial NAND Device command */
|
|
#define SERIAL_NAND_CMD_READ_FROM_CACHE_X4 0x6B
|
|
#define SERIAL_NAND_CMD_READ_FROM_CACHE_DUAL_IO 0xBB
|
|
#define SERIAL_NAND_CMD_READ_FROM_CACHE_QUAD_IO 0xEB
|
|
#define SERIAL_NAND_CMD_READ_ID 0x9F
|
|
#define SERIAL_NAND_CMD_PROGRAM_LOAD 0x02
|
|
#define SERIAL_NAND_CMD_PROGRAM_LOAD_X4 0x32
|
|
#define SERIAL_NAND_CMD_PROGRAM_EXECUTE 0x10
|
|
#define SERIAL_NAND_CMD_PROGRAM_LOAD_RND_DATA 0x84
|
|
#define SERIAL_NAND_CMD_PROGRAM_LOAD_RND_DATA_X4 0xC4 /* Or 0x34 */
|
|
#define SERIAL_NAND_CMD_PROGRAM_LOAD_QUAD_IO 0x72
|
|
#define SERIAL_NAND_CMD_BLOCK_ERASE 0xD8
|
|
#define SERIAL_NAND_CMD_RESET 0xFF
|
|
|
|
/* NAND Status errors */
|
|
#define NAND_FLASH_MPU_ERR (1 << 8)
|
|
#define NAND_FLASH_TIMEOUT_ERR (1 << 6)
|
|
#define NAND_FLASH_OP_ERR (1 << 4)
|
|
|
|
#define NAND_FLASH_ERR (NAND_FLASH_MPU_ERR | \
|
|
NAND_FLASH_TIMEOUT_ERR | \
|
|
NAND_FLASH_OP_ERR)
|
|
|
|
#define PROG_ERASE_OP_RESULT (1 << 7)
|
|
|
|
/* NAND buffer status */
|
|
#define NAND_BUFFER_UNCORRECTABLE (1 << 8)
|
|
#define NUM_ERRORS_MASK 0x0000001f
|
|
#define NUM_ERRORS(i) ((i) << 0)
|
|
|
|
#define DATA_CONSUMER_PIPE_INDEX 0
|
|
#define DATA_PRODUCER_PIPE_INDEX 1
|
|
#define CMD_PIPE_INDEX 2
|
|
#define BAM_STATUS_PIPE_INDEX 3
|
|
|
|
#define QPIC_AUTO_STATUS_DES_SIZE 12
|
|
|
|
/* Define BAM pipe lock groups for NANDc*/
|
|
#define P_LOCK_GROUP_0 0
|
|
|
|
/* Define BAM pipe lock super groups for NANDc
|
|
* Note: This is configured by TZ.
|
|
*/
|
|
#define P_LOCK_SUPERGROUP_0 0
|
|
#define P_LOCK_SUPERGROUP_1 1
|
|
|
|
#define ONFI_SIGNATURE 0x49464E4F
|
|
|
|
#define ONFI_CRC_POLYNOMIAL 0x8005
|
|
#define ONFI_CRC_INIT_VALUE 0x4F4E
|
|
|
|
#define ONFI_READ_PARAM_PAGE_ADDR_CYCLES 1
|
|
#define ONFI_READ_ID_ADDR_CYCLES 1
|
|
|
|
#define ONFI_READ_ID_CMD 0x90
|
|
#define ONFI_READ_PARAM_PAGE_CMD 0xEC
|
|
#define ONFI_READ_ID_ADDR 0x20
|
|
#define ONFI_READ_PARAM_PAGE_ADDR 0x00
|
|
|
|
#define NAND_CFG0_RAW_ONFI_ID 0x88000800
|
|
#define NAND_CFG0_RAW_ONFI_PARAM_PAGE 0x88040000
|
|
#define NAND_CFG1_RAW_ONFI_ID 0x0005045D
|
|
#define NAND_CFG1_RAW_ONFI_PARAM_PAGE 0x0005045D
|
|
#define NAND_CFG0 0x290409c0
|
|
#define NAND_CFG1 0x08045d5c
|
|
#define NAND_ECC_BCH_CFG 0x42040d10
|
|
#define NAND_Bad_Block 0x00000175
|
|
#define NAND_ECC_BUF_CFG 0x00000203
|
|
|
|
#define ONFI_READ_ID_BUFFER_SIZE 0x4
|
|
#define ONFI_READ_PARAM_PAGE_BUFFER_SIZE 0x200
|
|
#define ONFI_PARAM_PAGE_SIZE 0x100
|
|
|
|
#define NAND_8BIT_DEVICE 0x01
|
|
#define NAND_16BIT_DEVICE 0x02
|
|
|
|
#define NAND_CW_SIZE_4_BIT_ECC 528
|
|
#define NAND_CW_SIZE_8_BIT_ECC 532
|
|
/* Indicates the data bytes in the user data portion of the code word. */
|
|
#define USER_DATA_BYTES_PER_CW 512
|
|
|
|
#define NAND_CW_SPARE_SIZE_8_BIT_ECC (NAND_CW_SIZE_8_BIT_ECC - \
|
|
USER_DATA_BYTES_PER_CW)
|
|
|
|
/* Indicates the number of bytes covered by BCH ECC logic when
|
|
* a codeword is written to a NAND flash device.
|
|
* This is also the number of bytes that are part of the image in CW.
|
|
* 516 bytes = (512 bytes of user data and 4 bytes of spare data)
|
|
*/
|
|
#define DATA_BYTES_IN_IMG_PER_CW 516
|
|
|
|
#define NAND_CW_DIV_RIGHT_SHIFT 9
|
|
|
|
/* Number of max cw's the driver allows to flash. */
|
|
#define QPIC_NAND_MAX_CWS_IN_PAGE 10
|
|
|
|
/* Reset Values for Status registers */
|
|
#define NAND_FLASH_STATUS_RESET 0x00000020
|
|
#define NAND_READ_STATUS_RESET 0x000000C0
|
|
|
|
/* NANDc BAM pipe numbers */
|
|
#define DATA_CONSUMER_PIPE 0
|
|
#define DATA_PRODUCER_PIPE 1
|
|
#define CMD_PIPE 2
|
|
#define NAND_BAM_STATUS_PIPE 3
|
|
|
|
/* NANDc BAM pipe groups */
|
|
#define DATA_PRODUCER_PIPE_GRP 0
|
|
#define DATA_CONSUMER_PIPE_GRP 0
|
|
#define CMD_PIPE_GRP 1
|
|
#define NAND_BAM_STATUS_PIPE_GRP 0
|
|
|
|
/* NANDc EE */
|
|
#define QPIC_NAND_EE 0
|
|
|
|
/* NANDc max desc length. */
|
|
#define QPIC_NAND_MAX_DESC_LEN 0x7FFF
|
|
|
|
/* Register: NAND_CTRL */
|
|
#define BAM_MODE_EN 0x1
|
|
#define NANDC_READ_DELAY_COUNTER_VAL 0x340
|
|
|
|
/* Register: NAND_DEBUG */
|
|
#define BAM_MODE_BIT_RESET (1 << 31)
|
|
|
|
/* CMD Valid */
|
|
#define NAND_CMD_VALID_BASE 0x1D
|
|
|
|
#define NAND_ID_MAN(id) ((id) & 0xFF)
|
|
#define NAND_ID_DEV(id) (((id) >> 8) & 0xFF)
|
|
#define NAND_ID_CFG(id) (((id) >> 24) & 0xFF)
|
|
|
|
#define NAND_CFG_PAGE_SIZE(id) (((id) >> 0) & 0x3)
|
|
#define NAND_CFG_SPARE_SIZE(id) (((id) >> 2) & 0x3)
|
|
#define NAND_CFG_BLOCK_SIZE(id) (((id) >> 4) & 0x3)
|
|
|
|
#define CHUNK_SIZE 512
|
|
|
|
#define MB_TO_BYTES(mb) (((uint64_t)(mb)) << 20)
|
|
#define KB_TO_BYTES(kb) ((kb) << 10)
|
|
|
|
#define MTD_NAND_CHIP(mtd) ((struct nand_chip *)((mtd)->priv))
|
|
#define MTD_QPIC_NAND_DEV(mtd) (MTD_NAND_CHIP(mtd)->priv)
|
|
|
|
#ifdef CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
|
|
#define QPIC_BAM_DATA_FIFO_SIZE 512
|
|
#define QPIC_BAM_CMD_FIFO_SIZE 128
|
|
#define QPIC_BAM_STATUS_FIFO_SIZE 512
|
|
#else
|
|
#define QPIC_BAM_DATA_FIFO_SIZE 64
|
|
#define QPIC_BAM_CMD_FIFO_SIZE 64
|
|
#define QPIC_BAM_STATUS_FIFO_SIZE 64
|
|
#endif
|
|
|
|
#define QPIC_MAX_ONFI_MODES 4
|
|
#define QPIC_NUM_XFER_STEPS 7
|
|
|
|
enum qpic_verion{
|
|
QCA_QPIC_V1_4_20,
|
|
QCA_QPIC_V1_5_20,
|
|
QCA_QPIC_V2_1_1,
|
|
};
|
|
|
|
extern unsigned int qpic_frequency, qpic_phase, qpic_training_offset;
|
|
|
|
/* result type */
|
|
typedef enum {
|
|
NANDC_RESULT_SUCCESS = 0,
|
|
NANDC_RESULT_FAILURE = 1,
|
|
NANDC_RESULT_TIMEOUT = 2,
|
|
NANDC_RESULT_PARAM_INVALID = 3,
|
|
NANDC_RESULT_DEV_NOT_SUPPORTED = 4,
|
|
NANDC_RESULT_BAD_BLOCK = 5,
|
|
} nand_result_t;
|
|
|
|
enum nand_bad_block_value
|
|
{
|
|
NAND_BAD_BLK_VALUE_NOT_READ,
|
|
NAND_BAD_BLK_VALUE_IS_BAD,
|
|
NAND_BAD_BLK_VALUE_IS_GOOD,
|
|
};
|
|
|
|
enum nand_cfg_value
|
|
{
|
|
NAND_CFG_RAW,
|
|
NAND_CFG,
|
|
};
|
|
|
|
/* Structure for Serial nand parameter */
|
|
struct qpic_serial_nand_params {
|
|
u8 id[4];
|
|
u16 page_size;
|
|
u16 pgs_per_blk;
|
|
u32 spare_size;
|
|
u32 erase_blk_size;
|
|
u16 no_of_blocks;
|
|
u32 density;
|
|
u32 otp_region;
|
|
u8 no_of_addr_cycle;
|
|
u8 no_of_dies;
|
|
u8 num_bits_ecc_correctability;
|
|
u8 timing_mode_support;
|
|
bool quad_mode;
|
|
bool check_quad_config;
|
|
int prev_die_id;
|
|
u8 protec_bpx;
|
|
u64 pages_per_die;
|
|
const char *name;
|
|
};
|
|
|
|
struct onfi_param_page
|
|
{
|
|
uint32_t signature;
|
|
uint16_t rev;
|
|
uint16_t feature_supported;
|
|
uint16_t opt_cmd_supported;
|
|
uint8_t reserved_1[22];
|
|
uint8_t mib[12];
|
|
uint8_t device_model[20];
|
|
uint8_t manufacturer_id;
|
|
uint16_t date_code;
|
|
uint8_t reserved_2[13];
|
|
uint32_t data_per_pg;
|
|
uint16_t spare_per_pg;
|
|
uint32_t data_per_partial_pg;
|
|
uint16_t spare_per_partial_pg;
|
|
uint32_t pgs_per_blk;
|
|
uint32_t blks_per_LUN;
|
|
uint8_t num_LUN;
|
|
uint8_t num_addr_cycles;
|
|
uint8_t num_bits_per_cell;
|
|
uint16_t bad_blks_max_per_LUN;
|
|
uint16_t blk_endurance;
|
|
uint8_t guaranteed_vld_blks_at_start;
|
|
uint16_t blk_endurance_for_garunteed_vld_blks;
|
|
uint8_t num_prg_per_pg;
|
|
uint8_t partial_prog_attr;
|
|
uint8_t num_bits_ecc_correctability;
|
|
uint8_t num_interleaved_addr_bits;
|
|
uint8_t interleaved_op_attr;
|
|
uint8_t reserved_3[13];
|
|
uint8_t io_pin_capcacitance;
|
|
uint16_t timing_mode_support;
|
|
uint16_t prog_cache_timing_mode_support;
|
|
uint16_t max_pg_prog_time_us;
|
|
uint16_t max_blk_erase_time_us;
|
|
uint16_t max_pr_rd_time_us;
|
|
uint16_t min_chg_col_setup_time_us;
|
|
uint8_t reserved_4[23];
|
|
uint16_t vendor_rev;
|
|
uint8_t vendor_specific[88];
|
|
uint16_t interity_crc;
|
|
}__packed;
|
|
|
|
struct cfg_params
|
|
{
|
|
uint32_t addr0;
|
|
uint32_t addr1;
|
|
uint32_t cfg0;
|
|
uint32_t cfg1;
|
|
uint32_t cmd;
|
|
uint32_t ecc_cfg;
|
|
uint32_t addr_loc_0;
|
|
uint32_t exec;
|
|
};
|
|
|
|
struct onfi_probe_params
|
|
{
|
|
uint32_t vld;
|
|
uint32_t dev_cmd1;
|
|
struct cfg_params cfg;
|
|
};
|
|
|
|
/* This stucture is used to create a static list of devices we support.
|
|
* This include a subset of values defined in the flash_info struct as
|
|
* other values can be derived.
|
|
*/
|
|
struct flash_id
|
|
{
|
|
unsigned flash_id;
|
|
unsigned mask;
|
|
unsigned density;
|
|
unsigned widebus;
|
|
unsigned pagesize;
|
|
unsigned blksize;
|
|
unsigned oobsize;
|
|
unsigned ecc_8_bits;
|
|
};
|
|
|
|
/* Structure to hold the pipe numbers */
|
|
struct qpic_nand_bam_pipes
|
|
{
|
|
unsigned read_pipe;
|
|
unsigned write_pipe;
|
|
unsigned cmd_pipe;
|
|
#ifdef CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
|
|
unsigned status_pipe;
|
|
#endif
|
|
uint8_t read_pipe_grp;
|
|
uint8_t write_pipe_grp;
|
|
uint8_t cmd_pipe_grp;
|
|
#ifdef CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
|
|
uint8_t status_pipe_grp;
|
|
#endif
|
|
};
|
|
|
|
/* Structure to define the initial nand config */
|
|
struct qpic_nand_init_config
|
|
{
|
|
uint32_t nand_base;
|
|
uint32_t bam_base;
|
|
uint32_t ee;
|
|
uint32_t max_desc_len;
|
|
struct qpic_nand_bam_pipes pipes;
|
|
};
|
|
|
|
struct read_stats {
|
|
uint32_t flash_sts;
|
|
uint32_t buffer_sts;
|
|
uint32_t erased_cw_sts;
|
|
};
|
|
|
|
struct qpic_nand_dev {
|
|
unsigned id;
|
|
unsigned type;
|
|
unsigned vendor;
|
|
unsigned device;
|
|
unsigned page_size;
|
|
unsigned block_size;
|
|
unsigned spare_size;
|
|
unsigned num_blocks;
|
|
unsigned num_pages_per_blk;
|
|
unsigned num_pages_per_blk_mask;
|
|
unsigned widebus;
|
|
unsigned density;
|
|
unsigned cw_size;
|
|
unsigned cws_per_page;
|
|
unsigned bad_blk_loc;
|
|
unsigned ecc_bytes_hw;
|
|
unsigned spare_bytes;
|
|
unsigned bbm_size;
|
|
unsigned dev_cfg;
|
|
uint32_t cfg0;
|
|
uint32_t cfg1;
|
|
uint32_t cfg0_raw;
|
|
uint32_t cfg1_raw;
|
|
uint32_t ecc_bch_cfg;
|
|
#ifdef CONFIG_QPIC_SERIAL
|
|
bool quad_mode;
|
|
bool check_quad_config;
|
|
#endif
|
|
unsigned oob_per_page;
|
|
unsigned char *buffers;
|
|
unsigned char *pad_dat;
|
|
unsigned char *pad_oob;
|
|
unsigned char *zero_page;
|
|
unsigned char *zero_oob;
|
|
unsigned char *tmp_datbuf;
|
|
unsigned char *tmp_oobbuf;
|
|
#ifdef CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
|
|
bool multi_page_copy;
|
|
uint32_t multi_page_req_len;
|
|
unsigned char *status_buff;
|
|
uint32_t status_buf_size;
|
|
#endif
|
|
uint16_t timing_mode_support;
|
|
struct read_stats stats[QPIC_NAND_MAX_CWS_IN_PAGE];
|
|
};
|
|
|
|
void qpic_nand_init(qpic_nand_cfg_t *qpic_nand_cfg);
|
|
|
|
#endif
|