Matt Porter a3c3fabb0f arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx ... In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com>		2012-05-15 08:31:41 +02:00
..
cpu	arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx	2012-05-15 08:31:41 +02:00
dts	tegra: fdt: Add keyboard controller definition	2012-05-15 08:31:40 +02:00
include/asm	tegra: i2c: Add function to find DVC bus	2012-05-15 08:31:39 +02:00
lib	arm: restore fdt_fixup_ethernet call to do_bootm_linux	2012-04-23 22:11:18 +02:00
config.mk	Makefile: Add a 'checkthumb' rule	2012-05-15 08:31:26 +02:00