mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
91b2d3dea4
This patch updates the following: 1) Initializes I2C QUP clocks in U-Boot itself as required without depending on SBL. 2) Removes all CONFIG_IPQ9574_RUMI references. Change-Id: I1fb02861a70bd2b024122fff7810c3373cc2e1cd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
259 lines
8.4 KiB
C
259 lines
8.4 KiB
C
/*
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* Copyright (c) 2015-2016, 2018, 2021 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef IPQ9574_CLK_H
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#define IPQ9574_CLK_H
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#include <asm/arch-qca-common/uart.h>
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/* I2C clocks configuration */
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#ifdef CONFIG_IPQ9574_I2C
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#define BLSP1_QUP_BASE 0x078B5000
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#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x1802018
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#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x1802024
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR 0x180201C
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV (0x1F << 0)
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#define GCC_BLSP1_QUP_I2C_OFFSET_INC 0x1000
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#define GCC_BLSP1_QUP_I2C_APPS_CFG_RCGR(id) ((id < 1) ? \
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(GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR):\
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(GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id)))
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#define GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(id) ((id < 1) ? \
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(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR):\
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(GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id)))
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#define GCC_BLSP1_QUP_I2C_APPS_CBCR(id) ((id < 1) ? \
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(GCC_BLSP1_QUP1_I2C_APPS_CBCR):\
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(GCC_BLSP1_QUP1_I2C_APPS_CBCR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * id)))
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#define I2C_PORT_ID(reg) ((reg - BLSP1_QUP_BASE) / GCC_BLSP1_QUP_I2C_OFFSET_INC)
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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void i2c_clock_config(void);
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#endif
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#define GCC_BLSP1_UART1_BCR 0x1802028
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#define GCC_BLSP1_UART2_BCR 0x1803028
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#define GCC_BLSP1_UART3_BCR 0x1804028
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#define GCC_BLSP1_UART4_BCR 0x1805028
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#define GCC_BLSP1_UART5_BCR 0x1806028
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#define GCC_BLSP1_UART6_BCR 0x1807028
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#define GCC_BLSP1_UART_BCR(id) ((id < 1) ? \
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(GCC_BLSP1_UART1_BCR):\
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(GCC_BLSP1_UART1_BCR + (0x1000 * id)))
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#define GCC_BLSP1_UART_APPS_CMD_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x04)
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#define GCC_BLSP1_UART_APPS_CFG_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x08)
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#define GCC_BLSP1_UART_APPS_M(id) (GCC_BLSP1_UART_BCR(id) + 0x0c)
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#define GCC_BLSP1_UART_APPS_N(id) (GCC_BLSP1_UART_BCR(id) + 0x10)
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#define GCC_BLSP1_UART_APPS_D(id) (GCC_BLSP1_UART_BCR(id) + 0x14)
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#define GCC_BLSP1_UART_APPS_CBCR(id) (GCC_BLSP1_UART_BCR(id) + 0x18)
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#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000
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#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_UART_CFG_RCGR_MODE_SHIFT 12
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#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
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#define UART_RCGR_SRC_SEL 0x1
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#define UART_RCGR_SRC_DIV 0x0
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#define UART_RCGR_MODE 0x2
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#define UART_CMD_RCGR_UPDATE 0x1
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#define UART_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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/*
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* Qpic SPI Nand clock
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*/
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#define GCC_QPIC_IO_MACRO_CMD_RCGR 0x1832004
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#define GCC_QPIC_IO_MACRO_CFG_RCGR 0x1832008
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#define GCC_QPIC_IO_MACRO_CBCR 0x183200C
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#define GCC_QPIC_AHB_CBCR_ADDR 0x1832010
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#define GCC_QPIC_CBCR_ADDR 0x1832014
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#define GCC_QPIC_SLEEP_CBCR 0x1832018
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#define IO_MACRO_CLK_320_MHZ 320000000
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#define IO_MACRO_CLK_266_MHZ 266000000
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#define IO_MACRO_CLK_228_MHZ 228000000
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#define IO_MACRO_CLK_200_MHZ 200000000
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#define IO_MACRO_CLK_100_MHZ 100000000
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#define IO_MACRO_CLK_24MHZ 24000000
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#define QPIC_IO_MACRO_CLK 0
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#define QPIC_CORE_CLK 1
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#define XO_CLK_SRC 2
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#define GPLL0_CLK_SRC 3
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#define FB_CLK_BIT (1 << 4)
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#define UPDATE_EN 0x1
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/*
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* GCC-SDCC
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*/
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#define GCC_SDCC1_BCR 0x1833000
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#define GCC_SDCC1_APPS_CMD_RCGR 0x1833004
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#define GCC_SDCC1_APPS_CFG_RCGR 0x1833008
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#define GCC_SDCC1_APPS_M 0x183300C
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#define GCC_SDCC1_APPS_N 0x1833010
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#define GCC_SDCC1_APPS_D 0x1833014
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#define GCC_SDCC1_APPS_CBCR 0x183302C
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#define GCC_SDCC1_AHB_CBCR 0x1833034
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#define SDCC1_M_VAL 0x1
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#define SDCC1_N_VAL 0xFC
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#define SDCC1_D_VAL 0xFD
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#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV (0xB << 0)
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/*
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* USB
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*/
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#define GCC_USB_BCR 0x182C000
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#define GCC_USB0_MASTER_CMD_RCGR 0x182C004
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#define GCC_USB0_MASTER_CFG_RCGR 0x182C008
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#define GCC_USB0_AUX_CMD_RCGR 0x182C018
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#define GCC_USB0_AUX_CFG_RCGR 0x182C01C
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#define GCC_USB0_AUX_M 0x182C020
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#define GCC_USB0_AUX_N 0x182C024
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#define GCC_USB0_AUX_D 0x182C028
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#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x182C02C
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#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x182C030
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#define GCC_USB0_MOCK_UTMI_M 0x182C034
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#define GCC_USB0_MOCK_UTMI_N 0x182C038
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#define GCC_USB0_MOCK_UTMI_D 0x182C03C
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#define GCC_USB0_MASTER_CBCR 0x182C044
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#define GCC_USB0_AUX_CBCR 0x182C048
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#define GCC_USB0_MOCK_UTMI_CBCR 0x182C04C
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#define GCC_USB0_PIPE_CBCR 0x182C054
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#define GCC_USB0_SLEEP_CBCR 0x182C058
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#define GCC_USB0_PHY_CFG_AHB_CBCR 0x182C05C
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#define GCC_USB_0_BOOT_CLOCK_CTL 0x182C060
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#define GCC_QUSB2_0_PHY_BCR 0x182C068
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#define GCC_USB0_PHY_BCR 0x182C06C
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#define GCC_USB3PHY_0_PHY_BCR 0x182C070
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#define GCC_USB0_PHY_PIPE_MISC 0x182C074
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#define GCC_SNOC_USB_CBCR 0x182E058
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#define GCC_ANOC_USB_AXI_CBCR 0x182E084
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#define AUX_M 0x0
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#define AUX_N 0x0
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#define AUX_D 0x0
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#define SW_COLLAPSE_ENABLE (1 << 0)
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#define SW_OVERRIDE_ENABLE (1 << 2)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0x7 << 0)
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#define GCC_USB_MOCK_UTMI_SRC_SEL (0 << 8)
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#define GCC_USB_MOCK_UTMI_SRC_DIV (0x1 << 0)
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#define UTMI_M 0x1
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#define UTMI_N 0xFFFE
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#define UTMI_D 0xFFFD
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#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
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#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
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#define GCC_USB0_AUX_CFG_SRC_DIV (0 << 0)
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/*
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* PCIE
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*/
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#define GCC_PCIE_BASE 0x1828000
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#define GCC_PCIE_REG(_offset, _index) (GCC_PCIE_BASE + _offset +\
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(_index * 0x1000))
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#define GCC_PCIE_BCR 0x0
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#define GCC_PCIE_AUX_CMD_RCGR 0x4
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#define GCC_PCIE_AUX_CFG_RCGR 0x8
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#define GCC_PCIE_AUX_M 0xC
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#define GCC_PCIE_AUX_N 0x10
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#define GCC_PCIE_AUX_D 0x14
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#define GCC_PCIE_AXI_M_CMD_RCGR 0x18
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#define GCC_PCIE_AXI_M_CFG_RCGR 0x1C
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#define GCC_PCIE_AXI_S_CMD_RCGR 0x20
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#define GCC_PCIE_AXI_S_CFG_RCGR 0x24
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#define GCC_PCIE_RCHNG_CMD_RCGR 0x28
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#define GCC_PCIE_RCHNG_CFG_RCGR 0x2C
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#define GCC_PCIE_AHB_CBCR 0x30
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#define GCC_PCIE_AUX_CBCR 0x34
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#define GCC_PCIE_AXI_M_CBCR 0x38
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#define GCC_PCIE_AXI_S_CBCR 0x3C
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#define GCC_PCIE_AXI_S_BRIDGE_CBCR 0x40
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#define GCC_PCIE_PIPE_CBCR 0x44
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#define GCC_PCIE_BOOT_CLOCK_CTL 0x50
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#define GCC_PCIE_LINK_DOWN_BCR 0x54
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#define GCC_PCIE_MISC_RESET 0x58
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#define GCC_PCIEPHY_PHY_BCR 0x5C
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#define GCC_PCIE_PHY_BCR 0x60
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#define GCC_PCIE_PHY_PIPE_MISC 0x64
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#define GCC_SNOC_PCIE0_1LANE_S_CBCR 0x182E048
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#define GCC_SNOC_PCIE1_1LANE_S_CBCR 0x182E04C
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#define GCC_SNOC_PCIE2_2LANE_S_CBCR 0x182E050
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#define GCC_SNOC_PCIE3_2LANE_S_CBCR 0x182E054
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#define GCC_ANOC_PCIE0_1LANE_M_CBCR 0x182E07C
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#define GCC_ANOC_PCIE2_2LANE_M_CBCR 0x182E080
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#define GCC_ANOC_PCIE1_1LANE_M_CBCR 0x182E08C
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#define GCC_ANOC_PCIE3_2LANE_M_CBCR 0x182E090
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#define GCC_PCIE_AUX_CFG_RCGR_MN_MODE (2 << 12)
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#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0x13 << 0)
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#define GCC_PCIE_AXI_M_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_PCIE_AXI_M_CFG_RCGR_SRC_DIV_LANE2 (6 << 0)
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#define GCC_PCIE_AXI_M_CFG_RCGR_SRC_DIV_LANE1 (9 << 0)
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#define GCC_PCIE_AXI_S_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_PCIE_AXI_S_CFG_RCGR_SRC_DIV (9 << 0)
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define PIPE_CLK_ENABLE 0x4FF1
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#define CLK_DISABLE 0x0
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#define NOC_HANDSHAKE_FSM_EN (1 << 15)
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#define GCC_PCIE_RCHNG_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_PCIE_RCHNG_CFG_RCGR_SRC_DIV (0xF << 0)
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#define GCC_PCIE_PHY_PIPE_MISC_SRC_SEL (0x1 << 8)
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int uart_clock_config(struct ipq_serial_platdata *plat);
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#ifdef CONFIG_QPIC_NAND
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void qpic_set_clk_rate(unsigned int clk_rate, int blk_type,
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int req_clk_src_type);
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#endif
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(int id);
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void usb_clock_deinit(void);
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#endif
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void);
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void emmc_clock_reset(void);
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#endif
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#ifdef CONFIG_PCI_IPQ
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void pcie_v2_clock_init(int pcie_id);
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void pcie_v2_clock_deinit(int pcie_id);
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#endif
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#endif /*IPQ9574_CLK_H*/
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