u-boot-2016/drivers/clk
Md Sadre Alam b174865973 drivers: clk: ipq40xx: Clear divider value while doing deinit
This change will clear the divider value while doing deinit of
SD devices. In-order to clear the divider value we have to write
into register GCC_SDCC1_MISC.

Writing 0x0 to this register will clear the divider value which is
set, while doing initialization got SD devices.
Without this change, while kernel bootup we can see the below error.

error:
[3.529917] mmc0: Skipping voltage switch
[4.131741] mmc0: error -110 whilst initialising SD card.

Change-Id: Ifeca94ae09532a4b506e645cc9254e438179c886
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
2018-11-20 15:25:22 +05:30
..
clk-uclass.c dm: Add a clock uclass 2015-07-21 17:39:29 -06:00
clk_rk3036.c rockchip: rk3036: Add clock driver 2015-12-01 08:07:22 -07:00
clk_rk3288.c rockchip: rk3288: Add clock driver 2015-09-02 21:28:23 -06:00
clk_sandbox.c dm: test: Add tests for the clk uclass 2015-07-21 17:39:30 -06:00
ipq40xx_clk.c drivers: clk: ipq40xx: Clear divider value while doing deinit 2018-11-20 15:25:22 +05:30
ipq806x_clk.c ipq806x: set 48MHz clk for mmc data transfer mode 2018-03-19 11:47:02 +05:30
Kconfig clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLK 2015-08-18 13:46:01 -04:00
Makefile qca: ipq806x: Moved clock.c to driver/clk/ location. 2016-10-07 01:41:38 -07:00