mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
cb1e4ebe62
Added read & write bam pipe entires in all the ipq specific dtsi. Also, updated the spi bam code with generic code changes to enable the multiple spi support on all ipq chipsets. Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org> Signed-off-by: Ram Kumar D <ramd@codeaurora.org> Change-Id: Ibcdb9d2a9ff7a25f3d296ecdb1aca403511e07d7
337 lines
9.1 KiB
C
337 lines
9.1 KiB
C
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ40XX_H
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#define _IPQ40XX_H
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/*
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* Beat the system! tools/scripts/make-asm-offsets uses
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* the following hard-coded define for both u-boot's
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* ASM offsets and platform specific ASM offsets :(
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*/
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#ifndef DO_DEPS_ONLY
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#include <generated/asm-offsets.h>
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#endif
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#define CONFIG_IPQ40XX
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#define CONFIG_IPQ_NO_RELOC
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_VSNPRINTF
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#define CONFIG_IPQ40XX_UART
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_FIT_DISABLE_SHA256
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define V_PROMPT "(IPQ40xx) # "
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#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define TLMM_BASE 0x01000000
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#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
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#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
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#define HAVE_BLOCK_DEVICE
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_TEXT_BASE 0x87300000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
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CONFIG_SYS_MALLOC_LEN -\
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CONFIG_ENV_SIZE -\
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GENERATED_BD_INFO_SIZE)
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#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
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#define CONFIG_DTB_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (96 << 20))
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#define CONFIG_ROOTFS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20))
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_OF_LIBFDT 1
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#ifdef CONFIG_IPQ40XX_I2C
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#define CONFIG_SYS_I2C_QUP
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#define CONFIG_CMD_I2C
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#define CONFIG_DM_I2C
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#endif
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#define CONFIG_IPQ_APPSBL_IMG_TYPE 0x5
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#define CONFIG_SYS_DEVICE_NULLDEV
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/*
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* IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region.
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* CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting
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* address of WLAN Area.
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* TFTP file can only be written in Linux HLOS region and WLAN AREA.
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*/
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#define IPQ_TFTP_MIN_ADDR CONFIG_SYS_SDRAM_BASE
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#define CONFIG_TZ_END_ADDR 0x88000000
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#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + gd->ram_size)
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#define CONFIG_QCA_UBOOT_OFFSET 0x7000000
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#define CONFIG_UBOOT_END_ADDR 0x87400000
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#define CONFIG_IPQ40XX_ENV
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_OF_COMBINE 1
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#ifndef __ASSEMBLY__
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#include <compiler.h>
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extern loff_t board_env_offset;
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extern loff_t board_env_range;
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extern loff_t board_env_size;
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#if !defined(__ASSEMBLY__)
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#define INIT_STACK_SIZE 1024
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typedef struct {
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uint8_t uboot[1024 * 1024 - INIT_STACK_SIZE]; /* ~1MB */
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uint8_t init_stack[INIT_STACK_SIZE];
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uint8_t sbl[1024 * 1024]; /* 1 MB */
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uint8_t cnss_debug[6 * 1024 * 1024]; /* 6 MB */
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uint8_t tz_apps[3 * 1024 * 1024]; /* 3 MB */
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uint8_t smem[512 * 1024]; /* 512 KB */
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uint8_t tz[1536 * 1024]; /* 1.5 MB */
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} __attribute__ ((__packed__)) qca_mem_reserve_t;
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#define QCA_MEM_RESERVE_SIZE(x) sizeof(((qca_mem_reserve_t *)0)->x)
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#define QCA_MEM_RESERVE_BASE(x) \
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(CONFIG_SYS_TEXT_BASE + \
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((uint32_t)&(((qca_mem_reserve_t *)0)->x)))
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#endif/*__ASSEMBLY__*/
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#define CONFIG_QCA_SMEM_BASE 0x87e00000
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#define QCA_KERNEL_START_ADDR \
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(CONFIG_SYS_SDRAM_BASE + sizeof(qca_mem_reserve_t))
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#define QCA_DRAM_KERNEL_SIZE \
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(CONFIG_SYS_SDRAM_SIZE - sizeof(qca_mem_reserve_t))
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#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
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#endif
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#define CONFIG_FLASH_PROTECT
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#define CONFIG_CMD_FLASHWRITE
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/* Environment */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_ENV_OFFSET board_env_offset
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#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
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#define CONFIG_ENV_RANGE board_env_range
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#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (2048 << 10))
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x1300000
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + 0x100
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#define CONFIG_CMD_SOURCE 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_NULLDEV
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#define CONFIG_CMD_XIMG
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#define CONFIG_IPQ_ETH_INIT_DEFER
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/*
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* USB Support
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*/
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#ifdef CONFIG_USB_XHCI_IPQ
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_CMD_USB
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#define CONFIG_DOS_PARTITION
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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/*
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*Run command support
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*/
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#define CONFIG_CMD_RUN
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/*
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* SPI NAND SUPPORT
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*/
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#define CONFIG_IPQ40XX_SPI_NAND
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#ifdef CONFIG_IPQ40XX_SPI_NAND
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#define CONFIG_SPI_NAND
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#define CONFIG_SF_SPI_NAND_CS 1
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#define CONFIG_IPQ_SPI_NAND_INFO_IDX 1
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#endif
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#define CONFIG_QUP_SPI_USE_DMA 1
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/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
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* Cache flush and invalidation based on L1 cache, so the cache line
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* size is configured to 64 */
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_QCA_BAM 1
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/*
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* NAND Flash Configs104
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*/
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/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode107
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* CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode.108
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* BAM is enabled by default.109
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*/
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#define CONFIG_QPIC_NAND
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_MAX_NAND_DEVICE (CONFIG_IPQ_MAX_NAND_DEVICE + \
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CONFIG_IPQ_MAX_SPI_DEVICE)
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#define CONFIG_IPQ_MAX_BLSP_QUPS 2
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#define CONFIG_IPQ_MAX_SPI_DEVICE 2
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#define CONFIG_IPQ_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
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#define CONFIG_IPQ_SPI_NOR_INFO_IDX 2
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#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
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#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
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#define QCA_SPI_NOR_DEVICE "spi0.0"
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#define QCA_ROOT_FS_PART_NAME "rootfs"
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/*
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* SPI Flash Configs
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*/
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#define CONFIG_QCA_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SPI_FLASH_MACRONIX
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#define CONFIG_SPI_FLASH_GIGADEVICE
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_SPI_FLASH_USE_4K_SECTORS
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#define CONFIG_SPI_NOR_GENERIC
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED (48 * 1000 * 1000)
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#define CONFIG_SPI_FLASH_BAR 1
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_IPQ40XX_ESS 1
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#define CONFIG_IPQ40XX_EDMA 1
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#define CONFIG_NET_RETRY_COUNT 5
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_IPQ_MDIO 1
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#define CONFIG_QCA8075_PHY 1
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#define CONFIG_QCA8033_PHY 1
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#define CONFIG_MII
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#define CONFIG_CMD_MII
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#define CONFIG_IPADDR 192.168.1.11
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#define CONFIG_IPQ_NO_MACS 2
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_CMD_MTDPARTS
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#define NUM_ALT_PARTITION 8
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#define CONFIG_CMD_UBI
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#define CONFIG_RBTREE
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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#define CONFIG_IPQ_FDT_HIGH 0x87000000
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#define CONFIG_OF_BOARD_SETUP 1
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#ifdef CONFIG_OF_BOARD_SETUP
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#define DLOAD_DISABLE 0x1
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#define RESERVE_ADDRESS_START 0x87B00000 /*TZAPPS, SMEM and TZ Regions */
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#define RESERVE_ADDRESS_SIZE 0x500000
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#define SET_MAGIC 0x1
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#define CLEAR_MAGIC 0x0
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#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
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#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
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#define BOOT_VERSION 0
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#define TZ_VERSION 1
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#endif
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#define CONFIG_FDT_FIXUP_PARTITIONS
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#define CONFIG_BOOTCOMMAND "bootipq"
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_LIB_UUID
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#define CONFIG_SMP_CMD_SUPPORT
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#ifdef CONFIG_SMP_CMD_SUPPORT
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#define NR_CPUS 4
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#endif
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/*
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* CRASH DUMP ENABLE
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*/
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#define CONFIG_QCA_APPSBL_DLOAD 1
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#ifdef CONFIG_QCA_APPSBL_DLOAD
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#define CONFIG_CMD_TFTPPUT
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/* We will be uploading very big files */
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#undef CONFIG_NET_RETRY_COUNT
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#define CONFIG_NET_RETRY_COUNT 500
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#define IPQ_TEMP_DUMP_ADDR 0
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#endif
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#define CONFIG_QCA_KERNEL_CRASHDUMP_ADDRESS 0x87B00000
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#define CONFIG_CPU_CONTEXT_DUMP_SIZE 0x70000
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#define TLV_BUF_OFFSET 0x70000
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#define CONFIG_TLV_DUMP_SIZE 0x10000
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#define CONFIG_QCA_MMC 1
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#ifdef CONFIG_QCA_MMC
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#define CONFIG_MMC
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_SDHCI
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#define CONFIG_SDHCI_QCA
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#define CONFIG_GENERIC_MMC
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#define CONFIG_EFI_PARTITION
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SDHCI_SUPPORT
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#define CONFIG_MMC_ADMA
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#endif
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#define PCI_MAX_DEVICES 1
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#ifdef CONFIG_PCI_IPQ
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#define CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#undef CONFIG_IPQ_ROOTFS_AUTH
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#define CONFIG_IPQ_4B_ADDR_SWITCH_REQD
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#endif /* _IPQ40XX_H */
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