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u-boot-2016/arch/mips/lib
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Paul Burton 536cb7ce1a MIPS: refactor L1 cache config reads to a macro 
Reduce duplication between reading the configuration of the L1 dcache &
icache by performing both using a macro which calculates the appropriate
line & cache sizes from the coprocessor 0 Config1 register.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
..
ashldi3.c dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
ashrdi3.c dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
bootm.c MIPS: bootm: add bootstage reporting 2015-01-21 14:02:49 +01:00
cache.c MIPS: unify cache maintenance functions 2015-01-29 12:55:00 +01:00
cache_init.S MIPS: refactor L1 cache config reads to a macro 2015-01-29 12:55:01 +01:00
io.c MIPS: move mips_io_port_base out of board.c 2014-04-20 13:16:42 +02:00
libgcc.h dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
lshrdi3.c dm: mips: Import libgcc components from Linux 2012-08-17 20:13:48 +02:00
Makefile MIPS: unify cache initialization code 2015-01-29 12:55:01 +01:00