mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
32be07e796
Changes to use the C Flags pushed by the openwrt package directly from within the qca956x target sources is done. Change-Id: I4bacf9eb23ed442413d4b4f0833e8d1143aea77f Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
217 lines
6.4 KiB
C
217 lines
6.4 KiB
C
/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_BOOTDELAY 2 /* autoboot after 4 seconds */
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_MII 1
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#define CFG_CMD_MII 1
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#define CONFIG_COMMANDS 1
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#if pll
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#define CFG_PLL_FREQ (pll)
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#else
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#define CFG_PLL_FREQ CFG_PLL_750_400_250
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#endif
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#if ddr_cas
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#define CFG_DDR2_DRAGONFLY_CAS_LATENCY ddr_cas
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#else
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#define CFG_DDR2_DRAGONFLY_CAS_LATENCY 5
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#endif
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#if ATH_SGMII_FORCED
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#define ATH_SGMII_FORCED_MODE 1
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#endif
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#if CONFIG_AP152
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#define CFG_ATH_GMAC_NMACS 1
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#define CFG_ATH_GE1_IS_CONNECTED 1
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#define CONFIG_ATHRS_GMAC_SGMII 1
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#define ATH_S17_MAC0_SGMII 1
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#define CONFIG_ATHRS_GMAC_SGMII 1
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#define CONFIG_ATHRS17_PHY 1
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#define UART_RX18_TX22 1
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#define __CONFIG_BOARD_NAME ap152
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#define CONFIG_BOARD_NAME "ap152"
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#endif
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#if CONFIG_AP151
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#define CFG_ATH_GMAC_NMACS 2
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#define CFG_ATH_GE1_IS_CONNECTED 1
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#define CFG_ATHRS27_PHY 1
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#define UART_RX18_TX20 1
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#define __CONFIG_BOARD_NAME ap151
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#define CONFIG_BOARD_NAME "ap151"
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#endif
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_CUSTOM_BOARDINFO 1
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#define BOARDCAL 0x9fff0000
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#define CONFIG_TFTP_BLOCKSIZE 512
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_ICACHE_SIZE 65536
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_LOAD_ADDR 0x81000000
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#define CONFIG_LZMA 1
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#define CONFIG_ATHEROS 1
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#define CONFIG_IMAGE_FORMAT_LEGACY
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_INIT_SP_OFFSET 0xbd001800 // Redundant ?
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#define CFG_INIT_SRAM_SP_OFFSET 0xbd001800
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_FLASH_BASE 0x9f000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200}
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#define CONFIG_LAST_STAGE_INIT
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#define CONFIG_SYS_TEXT_BASE 0x9f000000
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 512
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "hush>"
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/* Timer Specific */
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#define CONFIG_SYS_MHZ 775
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/* Since the count is incremented every other tick, divide by 2 -- CFG_HZ*/
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#define CONFIG_SYS_MIPS_TIMER_FREQ ((CONFIG_SYS_MHZ * 1000000)/2)
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/*
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* The following #defines are needed to get flash environment right
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*/
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#define CONFIG_SYS_MONITOR_BASE 0x9f000000
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#define CONFIG_SYS_MONITOR_LEN (192 << 10)
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
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#ifndef FLASH_SIZE
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#define FLASH_SIZE 16
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#endif
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#if (FLASH_SIZE == 16)
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#elif (FLASH_SIZE == 8)
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#elif (FLASH_SIZE == 4)
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#elif (FLASH_SIZE == 2)
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#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#else
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# error "Invalid flash Size/sector "
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#endif
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#define CFG_FLASH_SECTOR_SIZE (64*1024)
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#if (FLASH_SIZE == 16)
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#define CFG_FLASH_SIZE 0x01000000 /* Total flash size */
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#elif (FLASH_SIZE == 8)
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#define CFG_FLASH_SIZE 0x00800000 /* max number of sectors on one chip */
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#elif (FLASH_SIZE == 4)
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#define CFG_FLASH_SIZE 0x00400000 /* Total flash size */
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#elif (FLASH_SIZE == 2)
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#define CFG_FLASH_SIZE 0x00200000 /* Total flash size */
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#else
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# error "Invalid flash Size "
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#endif
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#if defined(CONFIG_ATH_NAND_BR) && defined(COMPRESSED_UBOOT)
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#define CFG_FLASH_BASE 0xa0100000
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#else
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/* NOR Flash start address */
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#define CFG_FLASH_BASE 0x9f000000
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#endif
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#ifdef COMPRESSED_UBOOT
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#define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
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#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
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#endif
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/*
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* Defines to change flash size on reboot
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*/
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#ifdef ENABLE_DYNAMIC_CONF
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#define UBOOT_FLASH_SIZE (256 * 1024)
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#define UBOOT_ENV_SEC_START (CFG_FLASH_BASE + UBOOT_FLASH_SIZE)
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#define CFG_FLASH_MAGIC 0xaabacada
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#define CFG_FLASH_MAGIC_F (UBOOT_ENV_SEC_START + CFG_FLASH_SECTOR_SIZE - 0x20)
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#define CFG_FLASH_SECTOR_SIZE_F *(volatile int *)(CFG_FLASH_MAGIC_F + 0x4)
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#define CFG_FLASH_SIZE_F *(volatile int *)(CFG_FLASH_MAGIC_F + 0x8) /* Total flash size */
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#define CFG_MAX_FLASH_SECT_F (CFG_FLASH_SIZE / CFG_FLASH_SECTOR_SIZE) /* max number of sectors on one chip */
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#else
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#define CFG_FLASH_SIZE_F CFG_FLASH_SIZE
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#define CFG_FLASH_SECTOR_SIZE_F CFG_FLASH_SECTOR_SIZE
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#endif
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE CFG_FLASH_SECTOR_SIZE //CFG_ENV_SIZE
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#define CONFIG_ENV_ADDR 0x9f040000
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#define CONFIG_SYS_TEXT_BASE 0x9f000000
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#define CONFIG_ATH_SOC 1
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#define CONFIG_MACH_QCA956x 1
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// DDR2
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// 0x40c3 25MHz
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// 0x4138 40MHz
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// DDR1
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// 0x4186 25Mhz
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// 0x4270 40Mhz
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#define CFG_DDR_REFRESH_VAL 0x4186
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#define CFG_DDR2_REFRESH_VAL 0x40c3
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#define CONFIG_PCI_CONFIG_DATA_IN_OTP
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#if defined(CONFIG_CUS249) || defined(CONFIG_TB753)
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#else
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#define CONFIG_PCI 1
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_USB 1
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#endif
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/*
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** Parameters defining the location of the calibration/initialization
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** information for the two Merlin devices.
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** NOTE: **This will change with different flash configurations**
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*/
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#define WLANCAL 0x9fff1000
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/* For Merlin, both PCI, PCI-E interfaces are valid */
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#define ATH_ART_PCICFG_OFFSET 12
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