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MIPS: qca956x: Modify target files to use compile flags directly

Browse source 
Changes to use the C Flags pushed by the openwrt package directly
from within the qca956x target sources is done.

Change-Id: I4bacf9eb23ed442413d4b4f0833e8d1143aea77f
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
This commit is contained in:
Prabhu Jayakumar 2017-01-06 18:58:22 +05:30
parent 290b4e0b2d
commit 32be07e796
9 changed files with 227 additions and 219 deletions
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4
board/qca/mips32/common/ath_pci.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -201,7 +201,7 @@ void plat_dev_init(void)
** \return N/A
*/
#ifdef COMPRESSED_UBOOT
#if COMPRESSED_UBOOT
# define PCI_INIT_RET_TYPE int
# define PCI_INIT_RETURN return 0
#else

47
board/qca/mips32/qca956x/board956x.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -23,7 +23,7 @@
extern int ath_ddr_initial_config(uint32_t refresh);
extern int ath_ddr_find_size(void);
#ifdef COMPRESSED_UBOOT
#if COMPRESSED_UBOOT
# define prmsg(...)
# define args char *s
# define board_str(a) do { \
@ -98,8 +98,8 @@ ath_usb2_initial_config(void)
void ath_gpio_config(void)
{
#if defined(CONFIG_CUS249)
/* Turn on System LED GPIO18 for CUS249 */
ath_reg_rmw_clear(GPIO_OUT_ADDRESS, (1 << 18));
/* Turn on System LED GPIO18 for CUS249 */
ath_reg_rmw_clear(GPIO_OUT_ADDRESS, (1 << 18));
#endif
/* Turn off JUMPST_LED and 5Gz LED during bootup */
// ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 15));
@ -122,7 +122,10 @@ ath_mem_config(void)
tap = (uint32_t *)TAP_CONTROL_0_ADDRESS;
prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n",
tap[0], tap[1], tap[2], tap[3]);
ath_reg_rd(TAP_CONTROL_0_ADDRESS),
ath_reg_rd(TAP_CONTROL_1_ADDRESS),
ath_reg_rd(TAP_CONTROL_2_ADDRESS),
ath_reg_rd(TAP_CONTROL_3_ADDRESS));
/* Take WMAC out of reset */
reg32 = ath_reg_rd(RST_RESET_ADDRESS);
@ -134,27 +137,25 @@ ath_mem_config(void)
ath_usb1_initial_config();
ath_usb2_initial_config();
#else
//turn off not support interface register
reg32 = ath_reg_rd(RST_RESET_ADDRESS);
reg32 = reg32 | RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1);
ath_reg_wr_nf(RST_RESET_ADDRESS, reg32);
reg32 = ath_reg_rd(RST_CLKGAT_EN_ADDRESS);
reg32 = reg32 & ~(RST_CLKGAT_EN_PCIE_EP_SET(1) | RST_CLKGAT_EN_PCIE_RC_SET(1) |
RST_CLKGAT_EN_PCIE_RC2_SET(1) | RST_CLKGAT_EN_CLK100_PCIERC_SET(1) |
RST_CLKGAT_EN_CLK100_PCIERC2_SET(1) | RST_CLKGAT_EN_USB1_SET(1) |
RST_CLKGAT_EN_USB2_SET(1));
ath_reg_wr_nf(RST_CLKGAT_EN_ADDRESS, reg32);
reg32 = ath_reg_rd(RST_RESET2_ADDRESS);
reg32 = reg32 | RST_RESET2_USB_PHY2_PLL_PWD_EXT_SET(1);
ath_reg_wr_nf(RST_RESET2_ADDRESS, reg32);
//turn off not support interface register
reg32 = ath_reg_rd(RST_RESET_ADDRESS);
reg32 = reg32 | RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1);
ath_reg_wr_nf(RST_RESET_ADDRESS, reg32);
reg32 = ath_reg_rd(RST_CLKGAT_EN_ADDRESS);
reg32 = reg32 & ~(RST_CLKGAT_EN_PCIE_EP_SET(1) | RST_CLKGAT_EN_PCIE_RC_SET(1) |
RST_CLKGAT_EN_PCIE_RC2_SET(1) | RST_CLKGAT_EN_CLK100_PCIERC_SET(1) |
RST_CLKGAT_EN_CLK100_PCIERC2_SET(1) | RST_CLKGAT_EN_USB1_SET(1) |
RST_CLKGAT_EN_USB2_SET(1));
ath_reg_wr_nf(RST_CLKGAT_EN_ADDRESS, reg32);
reg32 = ath_reg_rd(RST_RESET2_ADDRESS);
reg32 = reg32 | RST_RESET2_USB_PHY2_PLL_PWD_EXT_SET(1);
ath_reg_wr_nf(RST_RESET2_ADDRESS, reg32);
ath_reg_wr_nf(BIAS4_ADDRESS, 0x6df6ffe0);
ath_reg_wr_nf(BIAS5_ADDRESS, 0x7ffffffe);
ath_reg_wr_nf(BIAS4_ADDRESS, 0x6df6ffe0);
ath_reg_wr_nf(BIAS5_ADDRESS, 0x7ffffffe);
#endif
ath_gpio_config();
#endif /* !defined(CONFIG_ATH_EMULATION) */
return ath_ddr_find_size();
}
@ -163,7 +164,7 @@ phys_size_t initdram(int board_type)
return (ath_mem_config());
}
int checkboard(args)
int checkboard(args)
{
board_str(CONFIG_BOARD_NAME);
return 0;

65
board/qca/mips32/qca956x/extra.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -30,39 +30,40 @@ ath_get_nand_cal_data(void)
{
extern unsigned long long ath_nand_get_cal_offset(const char *ba);
ulong off,size;
int ret;
static u_char nand_cal_data[256 * 1024];
nand_info_t *nand;
ulong off,size;
int ret;
static u_char nand_cal_data[256 * 1024];
nand_info_t *nand;
/*
* caldata partition is of 128k
*
*/
nand = &nand_info[nand_curr_device];
size = nand->erasesize;
/*
* caldata partition is of 128k
*
*/
/*
* Get the Offset of Caldata partition
*/
off = ath_nand_get_cal_offset(getenv("bootargs"));
if(off == ATH_CAL_OFF_INVAL) {
printf("Invalid CAL offset \n");
return 1;
}
nand = &nand_info[nand_curr_device];
size = nand->erasesize;
/*
* Get the values from flash, and program into the MAC address
* registers
*/
ret = nand_read(nand, (loff_t)off, &size, nand_cal_data);
printf(" %d bytes %s: %s\n", size,
"read", ret ? "ERROR" : "OK");
if(ret != 0 ) {
return NULL;
}
/*
* Get the Offset of Caldata partition
*/
return nand_cal_data;
off = ath_nand_get_cal_offset(getenv("bootargs"));
if(off == ATH_CAL_OFF_INVAL) {
printf("Invalid CAL offset \n");
return 1;
}
/*
* Get the values from flash, and program into the MAC address
* registers
*/
ret = nand_read(nand, (loff_t)off, &size, nand_cal_data);
printf(" %d bytes %s: %s\n", size,
"read", ret ? "ERROR" : "OK");
if(ret != 0 ) {
return NULL;
}
return nand_cal_data;
}
#endif
@ -78,9 +79,9 @@ int ath_set_tuning_caps(void)
uint32_t val;
#ifdef CONFIG_ATH_NAND_BR
eep = (ar9300_eeprom_t *)ath_get_nand_cal_data();
eep = (ar9300_eeprom_t *)ath_get_nand_cal_data();
#else
eep = (ar9300_eeprom_t *)WLANCAL;
eep = (ar9300_eeprom_t *)WLANCAL;
#endif /* CONFIG_ATH_NAND_BR */
val = XTAL_TCXODET_SET(0x0) |
XTAL_XTAL_CAPINDAC_SET(0x4b) |

172
board/qca/mips32/qca956x/init-956x.c
View file

@ -245,12 +245,14 @@ int /* ram type */
ath_ddr_initial_config(uint32_t refresh)
{
#if !defined(CONFIG_ATH_NAND_BR) && !defined(CONFIG_ATH_EMULATION)
int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val,
mod_val_init, cycle_val, tap_val, type, ctl_config;
uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F;
uint32_t bootstrap;
uint32_t *pll_config = (unsigned *)PLL_CONFIG_VAL_F;
uint32_t bootstrap;
#if !defined(CONFIG_DISPLAY_BOARDINFO)
prmsg("\nsri\n");
#endif
bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS);
@ -307,8 +309,8 @@ ath_ddr_initial_config(uint32_t refresh)
break;
}
#if 0
if (*pll == PLL_MAGIC) {
uint32_t cas = pll[5];
if (*pll_config == PLL_MAGIC) {
uint32_t cas = pll_config[5];
if (cas == 3 || cas == 4) {
cas = (cas * 2) + 2;
ddr_config &= ~(DDR_CONFIG_CAS_LATENCY_MSB_MASK |
@ -316,7 +318,7 @@ ath_ddr_initial_config(uint32_t refresh)
ddr_config |= DDR_CONFIG_CAS_LATENCY_SET(cas & 0x7) |
DDR_CONFIG_CAS_LATENCY_MSB_SET((cas >> 3) & 1);
cas = pll[5];
cas = pll_config[5];
ddr_config2 &= ~DDR_CONFIG2_GATE_OPEN_LATENCY_MASK;
ddr_config2 |= DDR_CONFIG2_GATE_OPEN_LATENCY_SET((2 * cas) + 1);
@ -466,7 +468,7 @@ void
ath_sys_frequency()
{
#if !defined(CONFIG_ATH_EMULATION)
unsigned int rdata, i;
unsigned int rdata, i;
unsigned int cpu_pll_low_int, cpu_pll_low_frac, cpu_pll_high_int, cpu_pll_high_frac;
unsigned int ddr_pll_low_int, ddr_pll_low_frac, ddr_pll_high_int, ddr_pll_high_frac;
unsigned int cpu_clk_low, cpu_clk_high;
@ -479,13 +481,13 @@ ath_sys_frequency()
/* CPU_PLL_CONFIG, CPU_PLL_CONFIG1, CPU_PLL_DITHER1, CPU_PLL_DITHER2 */
unsigned int cpu_pllpwd, cpu_outdiv, cpu_Refdiv, cpu_Nint;
unsigned int cpu_dither_en, cpu_NFrac_Min, cpu_NFrac_Max;
unsigned int cpu_NFrac_Min_17_5, cpu_NFrac_Min_4_0;
unsigned int cpu_NFrac_Max_17_5, cpu_NFrac_Max_4_0;
unsigned int cpu_NFrac_Min_17_5, cpu_NFrac_Min_4_0;
unsigned int cpu_NFrac_Max_17_5, cpu_NFrac_Max_4_0;
/* DDR_PLL_CONFIG, DDR_PLL_CONFIG1, DDR_PLL_DITHER1, DDR_PLL_DITHER2 */
unsigned int ddr_pllpwd, ddr_outdiv, ddr_Refdiv, ddr_Nint;
unsigned int ddr_dither_en, ddr_NFrac_Min, ddr_NFrac_Max;
unsigned int ddr_NFrac_Min_17_5, ddr_NFrac_Min_4_0;
unsigned int ddr_NFrac_Max_17_5, ddr_NFrac_Max_4_0;
unsigned int ddr_NFrac_Min_17_5, ddr_NFrac_Min_4_0;
unsigned int ddr_NFrac_Max_17_5, ddr_NFrac_Max_4_0;
static uint32_t ath_cpu_freq, ath_ddr_freq, ath_ahb_freq;
#endif
uint32_t ref_clk;
@ -542,13 +544,13 @@ ath_sys_frequency()
rdata = ath_reg_rd(CPU_PLL_DITHER1_ADDRESS);
cpu_dither_en = CPU_PLL_DITHER1_DITHER_EN_GET(rdata);
cpu_NFrac_Min = CPU_PLL_DITHER1_NFRAC_MIN_GET(rdata);
cpu_NFrac_Min_17_5 = (cpu_NFrac_Min >> 5) & 0x1fff;
cpu_NFrac_Min_4_0 = cpu_NFrac_Min & 0x1f;
cpu_NFrac_Min_17_5 = (cpu_NFrac_Min >> 5) & 0x1fff;
cpu_NFrac_Min_4_0 = cpu_NFrac_Min & 0x1f;
rdata = ath_reg_rd(CPU_PLL_DITHER1_ADDRESS);
cpu_NFrac_Max = CPU_PLL_DITHER2_NFRAC_MAX_GET(rdata);
cpu_NFrac_Max_17_5 = (cpu_NFrac_Max >> 5) & 0x1fff;
cpu_NFrac_Max_4_0 = cpu_NFrac_Max & 0x1f;
cpu_NFrac_Max_17_5 = (cpu_NFrac_Max >> 5) & 0x1fff;
cpu_NFrac_Max_4_0 = cpu_NFrac_Max & 0x1f;
rdata = ath_reg_rd(DDR_PLL_CONFIG_ADDRESS);
ddr_pllpwd = DDR_PLL_CONFIG_PLLPWD_GET(rdata);
@ -561,95 +563,95 @@ ath_sys_frequency()
rdata = ath_reg_rd(DDR_PLL_DITHER1_ADDRESS);
ddr_dither_en = DDR_PLL_DITHER1_DITHER_EN_GET(rdata);
ddr_NFrac_Min = DDR_PLL_DITHER1_NFRAC_MIN_GET(rdata);
ddr_NFrac_Min_17_5 = (ddr_NFrac_Min >> 5) & 0x1fff;
ddr_NFrac_Min_4_0 = ddr_NFrac_Min & 0x1f;
ddr_NFrac_Min_17_5 = (ddr_NFrac_Min >> 5) & 0x1fff;
ddr_NFrac_Min_4_0 = ddr_NFrac_Min & 0x1f;
rdata = ath_reg_rd(DDR_PLL_DITHER1_ADDRESS);
ddr_NFrac_Max = DDR_PLL_DITHER2_NFRAC_MAX_GET(rdata);
ddr_NFrac_Max_17_5 = (ddr_NFrac_Max >> 5) & 0x1fff;
ddr_NFrac_Max_4_0 = ddr_NFrac_Max & 0x1f;
ddr_NFrac_Max_17_5 = (ddr_NFrac_Max >> 5) & 0x1fff;
ddr_NFrac_Max_4_0 = ddr_NFrac_Max & 0x1f;
/* CPU PLL */
i = (ref_clk/cpu_Refdiv);
i = (ref_clk/cpu_Refdiv);
cpu_pll_low_int = i*cpu_Nint;
cpu_pll_high_int = cpu_pll_low_int;
cpu_pll_low_int = i*cpu_Nint;
cpu_pll_high_int = cpu_pll_low_int;
cpu_pll_low_frac = (i/(25*32))*((cpu_NFrac_Min_17_5*25 + cpu_NFrac_Min_4_0)/(8192/32));
cpu_pll_high_frac = (i/(25*32))*((cpu_NFrac_Max_17_5*25 + cpu_NFrac_Max_4_0)/(8192/32));
cpu_pll_low_frac = (i/(25*32))*((cpu_NFrac_Min_17_5*25 + cpu_NFrac_Min_4_0)/(8192/32));
cpu_pll_high_frac = (i/(25*32))*((cpu_NFrac_Max_17_5*25 + cpu_NFrac_Max_4_0)/(8192/32));
if (!cpu_dither_en || cpu_pll_high_frac <= cpu_pll_low_frac) {
cpu_pll_high_frac = cpu_pll_low_frac;
}
if (!cpu_dither_en || cpu_pll_high_frac <= cpu_pll_low_frac) {
cpu_pll_high_frac = cpu_pll_low_frac;
}
/* DDR PLL */
i = (ref_clk/ddr_Refdiv);
/* DDR PLL */
i = (ref_clk/ddr_Refdiv);
ddr_pll_low_int = i*ddr_Nint;
ddr_pll_high_int = ddr_pll_low_int;
ddr_pll_low_int = i*ddr_Nint;
ddr_pll_high_int = ddr_pll_low_int;
ddr_pll_low_frac = (i/(25*32))*((ddr_NFrac_Min_17_5*25 + ddr_NFrac_Min_4_0)/(8192/32));
ddr_pll_high_frac = (i/(25*32))*((ddr_NFrac_Max_17_5*25 + ddr_NFrac_Max_4_0)/(8192/32));
ddr_pll_low_frac = (i/(25*32))*((ddr_NFrac_Min_17_5*25 + ddr_NFrac_Min_4_0)/(8192/32));
ddr_pll_high_frac = (i/(25*32))*((ddr_NFrac_Max_17_5*25 + ddr_NFrac_Max_4_0)/(8192/32));
if (!ddr_dither_en || ddr_pll_high_frac <= ddr_pll_low_frac) {
ddr_pll_high_frac = ddr_pll_low_frac;
}
if (!ddr_dither_en || ddr_pll_high_frac <= ddr_pll_low_frac) {
ddr_pll_high_frac = ddr_pll_low_frac;
}
/* CPU Clock, DDR Clock, AHB Clock (before post div) */
if (cpu_ddr_clk_from_cpupll) {
cpu_clk_low = cpu_pll_low_int + cpu_pll_low_frac;
cpu_clk_high = cpu_pll_high_int + cpu_pll_high_frac;
/* CPU Clock, DDR Clock, AHB Clock (before post div) */
if (cpu_ddr_clk_from_cpupll) {
cpu_clk_low = cpu_pll_low_int + cpu_pll_low_frac;
cpu_clk_high = cpu_pll_high_int + cpu_pll_high_frac;
if (cpu_outdiv != 0) {
cpu_clk_low /= (2*cpu_outdiv);
cpu_clk_high /= (2*cpu_outdiv);
}
if (cpu_outdiv != 0) {
cpu_clk_low /= (2*cpu_outdiv);
cpu_clk_high /= (2*cpu_outdiv);
}
ddr_clk_low = cpu_clk_low;
ddr_clk_high = cpu_clk_high;
} else if (cpu_ddr_clk_from_ddrpll) {
ddr_clk_low = ddr_pll_low_int + ddr_pll_low_frac;
ddr_clk_high = ddr_pll_high_int + ddr_pll_high_frac;
ddr_clk_low = cpu_clk_low;
ddr_clk_high = cpu_clk_high;
} else if (cpu_ddr_clk_from_ddrpll) {
ddr_clk_low = ddr_pll_low_int + ddr_pll_low_frac;
ddr_clk_high = ddr_pll_high_int + ddr_pll_high_frac;
if (ddr_outdiv != 0) {
ddr_clk_low /= (2*ddr_outdiv);
ddr_clk_high /= (2*ddr_outdiv);
}
if (ddr_outdiv != 0) {
ddr_clk_low /= (2*ddr_outdiv);
ddr_clk_high /= (2*ddr_outdiv);
}
cpu_clk_low = ddr_clk_low;
cpu_clk_high = ddr_clk_high;
} else {
cpu_clk_low = cpu_pll_low_int + cpu_pll_low_frac;
cpu_clk_high = cpu_pll_high_int + cpu_pll_high_frac;
ddr_clk_low = ddr_pll_low_int + ddr_pll_low_frac;
ddr_clk_high = ddr_pll_high_int + ddr_pll_high_frac;
cpu_clk_low = ddr_clk_low;
cpu_clk_high = ddr_clk_high;
} else {
cpu_clk_low = cpu_pll_low_int + cpu_pll_low_frac;
cpu_clk_high = cpu_pll_high_int + cpu_pll_high_frac;
ddr_clk_low = ddr_pll_low_int + ddr_pll_low_frac;
ddr_clk_high = ddr_pll_high_int + ddr_pll_high_frac;
if (cpu_outdiv != 0) {
cpu_clk_low /= (2*cpu_outdiv);
cpu_clk_high /= (2*cpu_outdiv);
}
if (cpu_outdiv != 0) {
cpu_clk_low /= (2*cpu_outdiv);
cpu_clk_high /= (2*cpu_outdiv);
}
if (ddr_outdiv != 0) {
ddr_clk_low /= (2*ddr_outdiv);
ddr_clk_high /= (2*ddr_outdiv);
}
}
if (ddr_outdiv != 0) {
ddr_clk_low /= (2*ddr_outdiv);
ddr_clk_high /= (2*ddr_outdiv);
}
}
if (ahbclk_from_ddrpll) {
ahb_clk_low = ddr_clk_low;
ahb_clk_high = ddr_clk_high;
} else {
ahb_clk_low = cpu_clk_low;
ahb_clk_high = cpu_clk_high;
}
if (ahbclk_from_ddrpll) {
ahb_clk_low = ddr_clk_low;
ahb_clk_high = ddr_clk_high;
} else {
ahb_clk_low = cpu_clk_low;
ahb_clk_high = cpu_clk_high;
}
/* CPU Clock, DDR Clock, AHB Clock */
cpu_clk_low /= (cpu_post_div + 1);
cpu_clk_high /= (cpu_post_div + 1);
ddr_clk_low /= (ddr_post_div + 1);
ddr_clk_high /= (ddr_post_div + 1);
ahb_clk_low /= (ahb_post_div + 1);
ahb_clk_high /= (ahb_post_div + 1);
/* CPU Clock, DDR Clock, AHB Clock */
cpu_clk_low /= (cpu_post_div + 1);
cpu_clk_high /= (cpu_post_div + 1);
ddr_clk_low /= (ddr_post_div + 1);
ddr_clk_high /= (ddr_post_div + 1);
ahb_clk_low /= (ahb_post_div + 1);
ahb_clk_high /= (ahb_post_div + 1);
ath_cpu_freq = cpu_clk_low;
ath_ddr_freq = ddr_clk_low;
@ -658,10 +660,8 @@ ath_sys_frequency()
//*ddr_clk_h = ddr_clk_high;
//*ahb_clk_h = ahb_clk_high;
#endif
prmsg("%s: cpu %u ddr %u ahb %u\n", __func__,
prmsg("%s: cpu %u ddr %u ahb %u\n", __func__,
ath_cpu_freq / 1000000,
ath_ddr_freq / 1000000,
ath_ahb_freq / 1000000);
}

130
board/qca/mips32/qca956x/qca-eth-956x.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -118,33 +118,33 @@ static int ath_gmac_recv(struct eth_device *dev)
mac = (ath_gmac_mac_t *)dev->priv;
for (;;) {
f = mac->fifo_rx[mac->next_rx];
if (ath_gmac_rx_owned_by_dma(f)) {
/* check if the current Descriptor is_empty is 1,But the DMAed count is not-zero
then move to desciprot where the packet is available */
dmaed_pkt = (ath_gmac_reg_rd(mac, 0x194) >> 16);
if (!dmaed_pkt) {
break ;
} else {
if (f->is_empty == 1) {
while ( count < NO_OF_RX_FIFOS ) {
if (++mac->next_rx >= NO_OF_RX_FIFOS) {
mac->next_rx = 0;
}
f = mac->fifo_rx[mac->next_rx];
/*
* Break on valid data in the desc by checking
* empty bit.
*/
if (!f->is_empty){
count = 0;
break;
}
count++;
}
}
}
}
f = mac->fifo_rx[mac->next_rx];
if (ath_gmac_rx_owned_by_dma(f)) {
/* check if the current Descriptor is_empty is 1,But the DMAed count is not-zero
then move to desciprot where the packet is available */
dmaed_pkt = (ath_gmac_reg_rd(mac, 0x194) >> 16);
if (!dmaed_pkt) {
break ;
} else {
if (f->is_empty == 1) {
while ( count < NO_OF_RX_FIFOS ) {
if (++mac->next_rx >= NO_OF_RX_FIFOS) {
mac->next_rx = 0;
}
f = mac->fifo_rx[mac->next_rx];
/*
* Break on valid data in the desc by checking
* empty bit.
*/
if (!f->is_empty){
count = 0;
break;
}
count++;
}
}
}
}
length = f->pkt_size;
@ -162,7 +162,6 @@ static int ath_gmac_recv(struct eth_device *dev)
ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(f));
ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, 1);
}
return (0);
}
@ -304,52 +303,49 @@ static void athr_gmac_sgmii_setup()
int status = 0, count = 0;
#ifdef ATH_SGMII_FORCED_MODE
ath_reg_wr(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_SPEED_SEL1_SET(1) |
MR_AN_CONTROL_PHY_RESET_SET(1) |
MR_AN_CONTROL_DUPLEX_MODE_SET(1));
udelay(10);
ath_reg_wr(SGMII_CONFIG_ADDRESS, SGMII_CONFIG_MODE_CTRL_SET(2) |
SGMII_CONFIG_FORCE_SPEED_SET(1) |
SGMII_CONFIG_SPEED_SET(2));
printf ("SGMII in forced mode\n");
ath_reg_wr(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_SPEED_SEL1_SET(1) |
MR_AN_CONTROL_PHY_RESET_SET(1) |
MR_AN_CONTROL_DUPLEX_MODE_SET(1));
udelay(10);
ath_reg_wr(SGMII_CONFIG_ADDRESS, SGMII_CONFIG_MODE_CTRL_SET(2) |
SGMII_CONFIG_FORCE_SPEED_SET(1) |
SGMII_CONFIG_SPEED_SET(2));
printf ("SGMII in forced mode\n");
#else
ath_reg_wr(SGMII_CONFIG_ADDRESS, SGMII_CONFIG_MODE_CTRL_SET(2));
ath_reg_wr(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_AN_ENABLE_SET(1)
|MR_AN_CONTROL_PHY_RESET_SET(1));
ath_reg_wr(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_AN_ENABLE_SET(1) |
MR_AN_CONTROL_PHY_RESET_SET(1));
ath_reg_wr(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_AN_ENABLE_SET(1));
#endif
/*
* SGMII reset sequence suggested by systems team.
*/
/*
* SGMII reset sequence suggested by systems team.
*/
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_RX_CLK_N_RESET);
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1)
|SGMII_RESET_RX_125M_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1) |
SGMII_RESET_RX_125M_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1)
|SGMII_RESET_TX_125M_N_SET(1)
|SGMII_RESET_RX_125M_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1) |
SGMII_RESET_TX_125M_N_SET(1) |
SGMII_RESET_RX_125M_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1)
|SGMII_RESET_TX_125M_N_SET(1)
|SGMII_RESET_RX_125M_N_SET(1)
|SGMII_RESET_RX_CLK_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1) |
SGMII_RESET_TX_125M_N_SET(1) |
SGMII_RESET_RX_125M_N_SET(1) |
SGMII_RESET_RX_CLK_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1)
|SGMII_RESET_TX_125M_N_SET(1)
|SGMII_RESET_RX_125M_N_SET(1)
|SGMII_RESET_RX_CLK_N_SET(1)
|SGMII_RESET_TX_CLK_N_SET(1));
ath_reg_wr(SGMII_RESET_ADDRESS, SGMII_RESET_HW_RX_125M_N_SET(1) |
SGMII_RESET_TX_125M_N_SET(1) |
SGMII_RESET_RX_125M_N_SET(1) |
SGMII_RESET_RX_CLK_N_SET(1) |
SGMII_RESET_TX_CLK_N_SET(1));
ath_reg_rmw_clear(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_PHY_RESET_SET(1));
ath_reg_rmw_clear(MR_AN_CONTROL_ADDRESS, MR_AN_CONTROL_PHY_RESET_SET(1));
/*
* WAR::Across resets SGMII link status goes to weird
* state.
@ -357,6 +353,7 @@ static void athr_gmac_sgmii_setup()
* for sure we are in bad state.
* Issue a PHY reset in MR_AN_CONTROL_ADDRESS to keep going.
*/
status = (ath_reg_rd(SGMII_DEBUG_ADDRESS) & 0xff);
while (!(status == 0xf || status == 0x10)) {
@ -371,7 +368,6 @@ static void athr_gmac_sgmii_setup()
}
printf("%s SGMII done\n",__func__);
}
static void ath_gmac_hw_start(ath_gmac_mac_t *mac)
@ -581,8 +577,8 @@ static int ath_gmac_setup_fifos(ath_gmac_mac_t *mac)
static void ath_gmac_halt(struct eth_device *dev)
{
ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv;
ath_gmac_reg_rmw_clear(mac, ATH_MAC_CFG1,(ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN));
ath_gmac_reg_wr(mac,ATH_MAC_FIFO_CFG_0,0x1f1f);
ath_gmac_reg_rmw_clear(mac, ATH_MAC_CFG1,(ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN));
ath_gmac_reg_wr(mac,ATH_MAC_FIFO_CFG_0,0x1f1f);
ath_gmac_reg_wr(mac,ATH_DMA_RX_CTRL, 0);
while (ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL));
}
@ -1011,7 +1007,7 @@ ath_gmac_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t da
int cpu_eth_init(bd_t *bis)
{
ath_gmac_enet_initialize(bis);
return 0;
ath_gmac_enet_initialize(bis);
return 0;
}

2
board/qca/mips32/qca956x/qca-eth-956x.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and

8
include/956x.h
View file

@ -28,7 +28,6 @@
#define is_qca956x() (1)
#define is_sco() (1)
#define CFG_PLL_FREQ CFG_PLL_775_650_258
#define CPU_PLL_CONFIG_UPDATING_MSB 31
#define CPU_PLL_CONFIG_UPDATING_LSB 31
@ -1021,8 +1020,7 @@
#define DDR_FSM_WAIT_CTRL_ADDRESS 0x180000e4
//#define TAP_CONTROL_0_ADDRESS 0x1800001c
#define TAP_CONTROL_0_ADDRESS 0xb800001c
#define TAP_CONTROL_0_ADDRESS 0x1800001c
#define TAP_CONTROL_1_ADDRESS 0x18000020
#define TAP_CONTROL_2_ADDRESS 0x18000024
#define TAP_CONTROL_3_ADDRESS 0x18000028
@ -4192,8 +4190,8 @@
#define __nint_to_mhz(n, ref) ((n) * (ref) * 1000000)
#define __cpu_hz_40(pll) (__nint_to_mhz(CPU_PLL_CONFIG1_NINT_GET(pll), 40))
#define __cpu_hz_25(pll) (__nint_to_mhz(CPU_PLL_CONFIG1_NINT_GET(pll), 25))
#define __cpu_hz_40(val) (__nint_to_mhz(CPU_PLL_CONFIG1_NINT_GET(val), 40))
#define __cpu_hz_25(val) (__nint_to_mhz(CPU_PLL_CONFIG1_NINT_GET(val), 25))
/* Since the count is incremented every other tick, divide by 2 */
#define CFG_HZ (__cpu_hz_25(CPU_PLL_CONFIG1_NINT_VAL) / 2)

2
include/atheros.h
View file

@ -98,7 +98,7 @@ int ath_uart_freq(void);
typedef unsigned int ath_reg_t;
#ifdef COMPRESSED_UBOOT
#if COMPRESSED_UBOOT
# define prmsg(...)
#else
# define prmsg printf

16
include/configs/qca956x.h
View file

@ -20,8 +20,21 @@
#define CFG_CMD_MII 1
#define CONFIG_COMMANDS 1
#define CFG_DDR2_DRAGONFLY_CAS_LATENCY 5
#if pll
#define CFG_PLL_FREQ (pll)
#else
#define CFG_PLL_FREQ CFG_PLL_750_400_250
#endif
#if ddr_cas
#define CFG_DDR2_DRAGONFLY_CAS_LATENCY ddr_cas
#else
#define CFG_DDR2_DRAGONFLY_CAS_LATENCY 5
#endif
#if ATH_SGMII_FORCED
#define ATH_SGMII_FORCED_MODE 1
#endif
#if CONFIG_AP152
#define CFG_ATH_GMAC_NMACS 1
@ -30,7 +43,6 @@
#define ATH_S17_MAC0_SGMII 1
#define CONFIG_ATHRS_GMAC_SGMII 1
#define CONFIG_ATHRS17_PHY 1
#define ATH_SGMII_FORCED_MODE 1
#define UART_RX18_TX22 1
#define __CONFIG_BOARD_NAME ap152
#define CONFIG_BOARD_NAME "ap152"