mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
43b55089db
Since only Q6/TME/TZ should have access to memnoc clock, so removing the MEMNOC clock enable sequence. Change-Id: Iee32a59c340cda794b8ee3c314be871ab749ff79 Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
374 lines
13 KiB
C
374 lines
13 KiB
C
/*
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* Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ5332_CLK_H
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#define _IPQ5332_CLK_H
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#include <asm/arch-qca-common/uart.h>
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/*
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* UART registers
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*/
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#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x180B004
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#define GCC_BLSP1_UART1_BCR 0x1802028
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#define GCC_BLSP1_UART2_BCR 0x1803028
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#define GCC_BLSP1_UART3_BCR 0x1804028
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#define GCC_BLSP1_UART_BCR(id) ((id < 1) ? \
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(GCC_BLSP1_UART1_BCR):\
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(GCC_BLSP1_UART1_BCR + (0x1000 * id)))
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#define GCC_BLSP1_UART_APPS_CMD_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x04)
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#define GCC_BLSP1_UART_APPS_CFG_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x08)
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#define GCC_BLSP1_UART_APPS_M(id) (GCC_BLSP1_UART_BCR(id) + 0x0c)
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#define GCC_BLSP1_UART_APPS_N(id) (GCC_BLSP1_UART_BCR(id) + 0x10)
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#define GCC_BLSP1_UART_APPS_D(id) (GCC_BLSP1_UART_BCR(id) + 0x14)
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#define GCC_BLSP1_UART_APPS_CBCR(id) (GCC_BLSP1_UART_BCR(id) + 0x18)
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#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000
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#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_UART_CFG_RCGR_MODE_SHIFT 12
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#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
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#define BLSP1_AHB_CLK_ENABLE 0x16
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#define UART_RCGR_SRC_SEL 0x1
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#define UART_RCGR_SRC_DIV 0x0
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#define UART_RCGR_MODE 0x2
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#define UART_CMD_RCGR_UPDATE 0x1
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#define UART_CMD_RCGR_ROOT_EN 0x2
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#define UART_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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/*
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* Qpic SPI Nand clock
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*/
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#define GCC_QPIC_IO_MACRO_CMD_RCGR 0x1832004
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#define GCC_QPIC_IO_MACRO_CFG_RCGR 0x1832008
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#define GCC_QPIC_IO_MACRO_CBCR 0x183200C
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#define GCC_QPIC_AHB_CBCR_ADDR 0x1832010
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#define GCC_QPIC_CBCR_ADDR 0x1832014
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#define GCC_QPIC_SREGR 0x1832018
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#define GCC_QPIC_SLEEP_CBCR 0x183201C
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#define IO_MACRO_CLK_320_MHZ 320000000
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#define IO_MACRO_CLK_266_MHZ 266000000
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#define IO_MACRO_CLK_228_MHZ 228000000
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#define IO_MACRO_CLK_200_MHZ 200000000
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#define IO_MACRO_CLK_100_MHZ 100000000
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#define IO_MACRO_CLK_24MHZ 24000000
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#define QPIC_IO_MACRO_CLK 0
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#define QPIC_CORE_CLK 1
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#define XO_CLK_SRC 2
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#define GPLL0_CLK_SRC 3
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#define FB_CLK_BIT (1 << 4)
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#define UPDATE_EN 0x1
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/*
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* GCC-SDCC Registers
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*/
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#define GCC_SDCC1_BCR 0x1833000
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#define GCC_SDCC1_APPS_CMD_RCGR 0x1833004
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#define GCC_SDCC1_APPS_CFG_RCGR 0x1833008
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#define GCC_SDCC1_APPS_M 0x183300C
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#define GCC_SDCC1_APPS_N 0x1833010
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#define GCC_SDCC1_APPS_D 0x1833014
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#define GCC_SDCC1_APPS_CBCR 0x183302C
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#define GCC_SDCC1_AHB_CBCR 0x1833034
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#define GCC_SDCC1_APPS_CFG_RCGR_MODE_SEL (2 << 12)
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#define GCC_SDCC1_APPS_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_SDCC1_APPS_CFG_RCGR_SRC_DIV (0xB << 0)
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/*
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* Ethernet Clocks
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*/
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#define GCC_QDSS_AT_CMD_RCGR 0x0182D004
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#define GCC_QDSS_AT_CFG_RCGR 0x0182D008
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#define QDSS_AT_SRC_SEL 1 << 8
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#define QDSS_AT_DIV_SEL 9 << 0
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#define GCC_PCNOC_BFDCD_CFG_RCGR 0x1831008
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#define GCC_PCNOC_BFDCD_CMD_RCGR 0x1831004
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#define PCCNOC_BFDCD_SRC_SEL 1 << 8
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#define PCCNOC_BFDCD_DIV_SEL 0xF << 0
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#define GCC_SYSTEM_NOC_BFDCD_CFG_RCGR 0x182E008
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#define GCC_SYSTEM_NOC_BFDCD_CMD_RCGR 0x182E004
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#define SYSTEM_NOC_BFDCD_SRC_SEL 2 << 8
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#define SYSTEM_NOC_BFDCD_DIV_SEL 8 << 0
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#define NSS_CC_PPE_CMD_RCGR 0x39B003E8
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#define NSS_CC_PPE_CFG_RCGR 0x39B003EC
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#define NSS_CC_PPE_SRC_SEL 0x6 << 8
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#define NSS_CC_PPE_DIV_SEL 1 << 0
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#define GCC_IM_SLEEP_CBCR 0x1834020
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#define NSS_CC_NSS_CSR_CBCR 0x39B005E8
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#define NSS_CC_NSSNOC_NSS_CSR_CBCR 0x39B005EC
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#define GCC_UNIPHY0_SYS_CBCR 0x181600C
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#define GCC_UNIPHY1_SYS_CBCR 0x1816018
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#define GCC_UNIPHY1_AHB_CBCR 0x181601C
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#define GCC_UNIPHY0_AHB_CBCR 0x1816010
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#define NSS_CC_NSSNOC_PPE_CBCR 0x39B00420
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#define GCC_MDIO_SLAVE_AHB_CBCR 0x181200C
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#define GCC_MDIO_MASTER_AHB_CBCR 0x1812004
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#define GCC_NSSCC_CBCR 0x1817034
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#define GCC_NSSNOC_NSSCC_CBCR 0x1817030
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#define PLL_POWER_ON_AND_RESET 0x9B780
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#define PLL_REFERENCE_CLOCK 0x9B784
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#define FREQUENCY_MASK 0xfffffdf0
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#define INTERNAL_48MHZ_CLOCK 0x7
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#define NSS_CC_CFG_CMD_RCGR 0x39B005E0
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#define NSS_CC_CFG_CFG_RCGR 0x39B005E4
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#define NSS_CC_SRC_SEL 2 << 8
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#define NSS_CC_DIV_SEL 0xF << 0
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#define GCC_NSSNOC_ATB_CLK 0x01817014
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#define GCC_NSSNOC_QOSGEN_REF_CLK 0x0181701C
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 0x01817020
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#define GCC_NSSNOC_SNOC_CBCR 0x01817028
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#define GCC_NSSCFG_CLK 0x0181702C
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#define GCC_NSSNOC_SNOC_1_CBCR 0x0181707C
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#define GCC_CMN_BLK_ADDR 0x0183A000
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#define GCC_CMN_BLK_AHB_CBCR_OFFSET 0x4
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#define GCC_CMN_BLK_SYS_CBCR_OFFSET 0x8
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#define GCC_CBCR_CLK_ENABLE 0x1
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#define NSS_CC_PPE_FREQUENCY_RCGR 0x39B003E8
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#define NSS_CC_PPE_SWITCH_CFG_ADDR 0x39B003F8
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#define NSS_CC_PPE_SWITCH_BTQ_ADDR 0x39B00400
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#define NSS_CC_PPE_SWITCH_CBCR 0x39B00408
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#define NSS_CC_PPE_SWITCH_CFG_CBCR 0x39B00410
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#define NSS_CC_PPE_EDMA_CBCR 0x39B00414
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#define NSS_CC_PPE_EDMA_CFG_CBCR 0x39B0041C
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#define NSS_CC_NSSNOC_PPE_CBCR 0x39B00420
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#define NSS_CC_NSSNOC_PPE_CFG_CBCR 0x39B00424
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#define GCC_PORT_MAC_ADDR 0x39B00428
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#define NSS_CC_PORT1_RX_CBCR 0x39B00480
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#define NSS_CC_UNIPHY_PORT1_RX_CBCR 0x39B004B4
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#define MDIO_50MHZ_CLK_BASE 0x7a00610
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#define GCC_USB_BCR 0x182C000
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#define GCC_USB0_MASTER_CMD_RCGR 0x182C004
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#define GCC_USB0_MASTER_CFG_RCGR 0x182C008
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#define GCC_USB0_MASTER_M 0x182C00C
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#define GCC_USB0_MASTER_N 0x182C010
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#define GCC_USB0_MASTER_D 0x182C014
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#define GCC_USB0_AUX_CMD_RCGR 0x182C018
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#define GCC_USB0_AUX_CFG_RCGR 0x182C01C
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#define GCC_USB0_AUX_M 0x182C020
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#define GCC_USB0_AUX_N 0x182C024
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#define GCC_USB0_AUX_D 0x182C028
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#define GCC_USB0_MOCK_UTMI_CMD_RCGR 0x182C02C
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#define GCC_USB0_MOCK_UTMI_CFG_RCGR 0x182C030
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#define GCC_USB0_MOCK_UTMI_M 0x182C034
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#define GCC_USB0_MOCK_UTMI_N 0x182C038
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#define GCC_USB0_MOCK_UTMI_D 0x182C03C
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#define GCC_USB0_MOCK_UTMI_DIV_CDIVR 0x182C040
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#define GCC_USB0_MASTER_CBCR 0x182C048
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#define GCC_USB0_MASTER_SREGR 0x182C04C
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#define GCC_USB0_AUX_CBCR 0x182C050
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#define GCC_USB0_MOCK_UTMI_CBCR 0x182C054
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#define GCC_USB0_SLEEP_CBCR 0x182C058
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#define GCC_USB0_PHY_CFG_AHB_CBCR 0x182C05C
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#define GCC_USB0_BOOT_CLOCK_CTL 0x182C060
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#define GCC_USB0_PHY_BCR 0x182C06C
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#define GCC_USB3PHY_0_PHY_BCR 0x182C070
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#define GCC_USB0_PHY_PIPE_MISC 0x182C074
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#define GCC_USB0_PIPE_CBCR 0x182C078
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#define GCC_USB0_LFPS_CMD_RCGR 0x182C07C
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#define GCC_USB0_LFPS_CFG_RCGR 0x182C080
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#define GCC_USB0_LFPS_M 0x182C084
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#define GCC_USB0_LFPS_N 0x182C088
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#define GCC_USB0_LFPS_D 0x182C08C
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#define GCC_USB0_LFPS_CBCR 0x182C090
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#define GCC_USB0_EUD_AT_CBCR 0x1830004
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#define GCC_USB0_BOOT_CLOCK_CTL 0x182C060
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#define GCC_QUSB2_0_PHY_BCR 0x182C068
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#define GCC_USB0_LFPS_CFG_SRC_SEL (0x1 << 8)
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#define GCC_USB0_LFPS_CFG_SRC_DIV (0x1F << 0)
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#define LFPS_M 0x1
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#define LFPS_N 0xFE
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#define LFPS_D 0xFD
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#define GCC_USB0_LFPS_MODE (0x2 << 12)
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#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
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#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
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#define GCC_USB0_AUX_CFG_SRC_DIV (0x17 << 0)
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#define AUX_M 0x0
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#define AUX_N 0x0
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#define AUX_D 0x0
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0x7 << 0)
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#define GCC_USB_MOCK_UTMI_MN_MODE (2 << 12)
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#define GCC_USB_MOCK_UTMI_SRC_SEL (1 << 8)
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#define GCC_USB_MOCK_UTMI_SRC_DIV (0x13 << 0)
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#define MOCK_UTMI_M 0x1
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#define MOCK_UTMI_N 0xFE
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#define MOCK_UTMI_D 0xFD
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#define PIPE_UTMI_CLK_SEL 0x1
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#define PIPE3_PHYSTATUS_SW (0x1 << 3)
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#define PIPE_UTMI_CLK_DIS (0x1 << 8)
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/*
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* PCIE
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* PCIE0 ---> PCIE3X1_0
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* PCIE1 ---> PCIE3X2
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* PCIE2 ---> PCIE3X1_1
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*/
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#define GCC_CONFIG_PCIE0 0
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#define GCC_CONFIG_PCIE1 1
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#define GCC_CONFIG_PCIE2 2
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#define GCC_SNOC_PCIE3_2LANE_S_CBCR 0x182E048
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#define GCC_SNOC_PCIE3_1LANE_S_CBCR 0x182E04C
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#define GCC_SNOC_PCIE3_1LANE_1_M_CBCR 0x182E050
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#define GCC_SNOC_PCIE3_2LANE_M_CBCR 0x182E07C
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#define GCC_SNOC_PCIE3_1LANE_M_CBCR 0x182E080
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#define GCC_SNOC_PCIE3_1LANE_1_S_CBCR 0x182E0AC
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#define GCC_PCIE3X2_BASE 0x1828000
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#define GCC_PCIE3X1_0_BASE 0x1829000
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#define GCC_PCIE3X1_1_BASE 0x182A000
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#define GCC_PCIE_AUX_CMD_RCGR 0x1828004
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#define GCC_PCIE_AUX_CFG_RCGR 0x1828008
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#define GCC_PCIE_AUX_M 0x182800C
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#define GCC_PCIE_AUX_N 0x1828010
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#define GCC_PCIE_AUX_D 0x1828014
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#define GCC_PCIE3X2_BCR (GCC_PCIE3X2_BASE+0x000)
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#define GCC_PCIE3X2_AXI_M_CMD_RCGR (GCC_PCIE3X2_BASE+0x018)
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#define GCC_PCIE3X2_AXI_M_CFG_RCGR (GCC_PCIE3X2_BASE+0x01C)
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#define GCC_PCIE3X2_AHB_CBCR (GCC_PCIE3X2_BASE+0x030)
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#define GCC_PCIE3X2_AXI_M_CBCR (GCC_PCIE3X2_BASE+0x038)
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#define GCC_PCIE3X2_AXI_M_SREGR (GCC_PCIE3X2_BASE+0x03C)
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#define GCC_PCIE3X2_AXI_S_CBCR (GCC_PCIE3X2_BASE+0x040)
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#define GCC_PCIE3X2_AXI_S_SREGR (GCC_PCIE3X2_BASE+0x044)
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#define GCC_PCIE3X2_AXI_S_BRIDGE_CBCR (GCC_PCIE3X2_BASE+0x048)
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#define GCC_PCIE3X2_PIPE_CBCR (GCC_PCIE3X2_BASE+0x068)
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#define GCC_PCIE3X2_AUX_CBCR (GCC_PCIE3X2_BASE+0x070)
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#define GCC_PCIE3X2_RCHG_CMD_RCGR (GCC_PCIE3X2_BASE+0x078)
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#define GCC_PCIE3X2_RCHG_CFG_RCGR (GCC_PCIE3X2_BASE+0x07C)
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#define GCC_PCIE3X2_PHY_AHB_CBCR (GCC_PCIE3X2_BASE+0x080)
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#define GCC_PCIE3X2_AXI_S_CMD_RCGR (GCC_PCIE3X2_BASE+0x084)
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#define GCC_PCIE3X2_AXI_S_CFG_RCGR (GCC_PCIE3X2_BASE+0x088)
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#define GCC_PCIE3X1_0_BCR (GCC_PCIE3X1_0_BASE+0x000)
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#define GCC_PCIE3X1_0_AXI_CMD_RCGR (GCC_PCIE3X1_0_BASE+0x018)
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#define GCC_PCIE3X1_0_AXI_CFG_RCGR (GCC_PCIE3X1_0_BASE+0x01C)
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#define GCC_PCIE3X1_0_AHB_CBCR (GCC_PCIE3X1_0_BASE+0x030)
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#define GCC_PCIE3X1_0_AXI_M_CBCR (GCC_PCIE3X1_0_BASE+0x038)
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#define GCC_PCIE3X1_0_AXI_M_SREGR (GCC_PCIE3X1_0_BASE+0x03C)
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#define GCC_PCIE3X1_0_AXI_S_CBCR (GCC_PCIE3X1_0_BASE+0x040)
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#define GCC_PCIE3X1_0_AXI_S_SREGR (GCC_PCIE3X1_0_BASE+0x044)
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#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CBCR (GCC_PCIE3X1_0_BASE+0x048)
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#define GCC_PCIE3X1_0_PIPE_CBCR (GCC_PCIE3X1_0_BASE+0x068)
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#define GCC_PCIE3X1_0_AUX_CBCR (GCC_PCIE3X1_0_BASE+0x070)
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#define GCC_PCIE3X1_PHY_AHB_CBCR (GCC_PCIE3X1_0_BASE+0x078)
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#define GCC_PCIE3X1_0_RCHG_CMD_RCGR (GCC_PCIE3X1_0_BASE+0x07C)
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#define GCC_PCIE3X1_0_RCHG_CFG_RCGR (GCC_PCIE3X1_0_BASE+0x080)
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#define GCC_PCIE3X1_1_BCR (GCC_PCIE3X1_1_BASE+0x000)
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#define GCC_PCIE3X1_1_AXI_CMD_RCGR (GCC_PCIE3X1_1_BASE+0x004)
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#define GCC_PCIE3X1_1_AXI_CFG_RCGR (GCC_PCIE3X1_1_BASE+0x008)
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#define GCC_PCIE3X1_1_AHB_CBCR (GCC_PCIE3X1_1_BASE+0x00C)
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#define GCC_PCIE3X1_1_AXI_M_CBCR (GCC_PCIE3X1_1_BASE+0x014)
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#define GCC_PCIE3X1_1_AXI_M_SREGR (GCC_PCIE3X1_1_BASE+0x018)
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#define GCC_PCIE3X1_1_AXI_S_CBCR (GCC_PCIE3X1_1_BASE+0x01C)
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#define GCC_PCIE3X1_1_AXI_S_SREGR (GCC_PCIE3X1_1_BASE+0x020)
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#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CBCR (GCC_PCIE3X1_1_BASE+0x024)
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#define GCC_PCIE3X1_1_PIPE_CBCR (GCC_PCIE3X1_1_BASE+0x068)
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#define GCC_PCIE3X1_1_AUX_CBCR (GCC_PCIE3X1_1_BASE+0x070)
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#define GCC_PCIE3X1_1_AUX_SREGR (GCC_PCIE3X1_1_BASE+0x074)
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#define GCC_PCIE3X1_1_RCHG_CMD_RCGR (GCC_PCIE3X1_1_BASE+0x078)
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#define GCC_PCIE3X1_1_RCHG_CFG_RCGR (GCC_PCIE3X1_1_BASE+0x07C)
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#define GCC_PCIE_AUX_CFG_RCGR_MN_MODE (0 << 12)
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#define GCC_PCIE_AUX_CFG_RCGR_SRC_SEL (0 << 8) /* SRC = XO */
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#define GCC_PCIE_AUX_CFG_RCGR_SRC_DIV (0x17 << 0)
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#define GCC_PCIE_AXI_CFG_RCGR_SRC_SEL (0x9 << 0)
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#define GCC_PCIE_AXI_CFG_RCGR_SRC_DIV (2 << 8)
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#define GCC_PCIE_AXI_M_CFG_RCGR_SRC_SEL (0x8 << 0)
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#define GCC_PCIE_AXI_M_CFG_RCGR_SRC_DIV (2 << 8)
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#define GCC_PCIE_AXI_S_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_PCIE_AXI_S_CFG_RCGR_SRC_DIV (9 << 0)
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#define GCC_PCIE3X2_AXI_S_CFG_RCGR_SRC_SEL (2 << 8)
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#define GCC_PCIE3X2_AXI_S_CFG_RCGR_SRC_DIV (9 << 0)
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#define GCC_PCIE_RCHG_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_PCIE_RCHG_CFG_RCGR_SRC_DIV (0xF << 0)
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define PIPE_CLK_ENABLE 0x4FF1
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#define CLK_DISABLE 0x0
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#define NOC_HANDSHAKE_FSM_EN (1 << 15)
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#define GCC_PCIE_PHY_PIPE_MISC_SRC_SEL (0x1 << 8)
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void);
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void emmc_clock_reset(void);
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#endif
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#ifdef CONFIG_PCI_IPQ
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void pcie_v2_clock_init(int pcie_id);
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void pcie_v2_clock_deinit(int pcie_id);
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#endif
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int uart_clock_config(struct ipq_serial_platdata *plat);
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#ifdef CONFIG_USB_XHCI_IPQ
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void usb_clock_init(void);
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void usb_clock_deinit(void);
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#endif
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enum uniphy_clk_type {
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NSS_PORT1_RX_CLK_E = 0,
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NSS_PORT1_TX_CLK_E,
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NSS_PORT2_RX_CLK_E,
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NSS_PORT2_TX_CLK_E,
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UNIPHY0_PORT1_RX_CLK_E,
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UNIPHY0_PORT1_TX_CLK_E,
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UNIPHY0_PORT2_RX_CLK_E,
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UNIPHY0_PORT2_TX_CLK_E,
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UNIPHYT_CLK_MAX,
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};
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void eth_clock_init(void);
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#endif /*IPQ5332_CLK_H*/
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