Rajkumar Ayyasamy 14fe9facff ipq806x: set 48MHz clk for mmc data transfer mode ... As 52Mhz clk does not have 50% dutycycle, setting 48MHz clk for mmc data transfer mode Change-Id: Id9c0ce07fe652df7d575c5ea11f1d83eab0fb24c Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>		2018-03-19 11:47:02 +05:30
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clk-uclass.c	dm: Add a clock uclass	2015-07-21 17:39:29 -06:00
clk_rk3036.c	rockchip: rk3036: Add clock driver	2015-12-01 08:07:22 -07:00
clk_rk3288.c	rockchip: rk3288: Add clock driver	2015-09-02 21:28:23 -06:00
clk_sandbox.c	dm: test: Add tests for the clk uclass	2015-07-21 17:39:30 -06:00
ipq40xx_clk.c	qca: move ARM specific files to another sublevel	2017-01-06 12:33:30 +05:30
ipq806x_clk.c	ipq806x: set 48MHz clk for mmc data transfer mode	2018-03-19 11:47:02 +05:30
Kconfig	clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLK	2015-08-18 13:46:01 -04:00
Makefile	qca: ipq806x: Moved clock.c to driver/clk/ location.	2016-10-07 01:41:38 -07:00