mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
32be07e796
Changes to use the C Flags pushed by the openwrt package directly from within the qca956x target sources is done. Change-Id: I4bacf9eb23ed442413d4b4f0833e8d1143aea77f Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
355 lines
8.7 KiB
C
355 lines
8.7 KiB
C
/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _ATHEROS_H
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#define _ATHEROS_H
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/*
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* Set everything to zero. The corresponding header will
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* undef and re-define the appropriate ones
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*/
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#define is_ar7100() (0)
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#define is_ar7240() (0)
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#define is_ar7241() (0)
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#define is_ar7242() (0)
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#define is_ar9330() (0)
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#define is_ar933x() (0)
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#define is_hornet() (0)
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#define is_ar934x() (0)
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#define is_wasp() (0)
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#define is_qca955x() (0)
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#define is_sco() (0)
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#define is_qca953x() (0)
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#define is_hb() (0)
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#define is_qca956x() (0)
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#define ATH_CONSOLE_BAUD 115200
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#define AR7240_REV_1_2 0xc2
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#ifdef CONFIG_ATH_EMULATION
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#define is_emu() (1)
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#else
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#define is_emu() (0)
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#endif
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#ifdef CONFIG_F1E_PHY
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#define is_f1e() 1
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#else
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#define is_f1e() 0
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#endif
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#ifdef CONFIG_F2E_PHY
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#define is_f2e() 1
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#else
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#define is_f2e() 0
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#endif
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#ifdef CONFIG_ATHRS16_PHY
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#define is_s16() 1
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#else
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#define is_s16() 0
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#endif
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#ifdef CONFIG_ATHRS17_PHY
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#define is_s17() 1
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#else
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#define is_s17() 0
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#endif
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#ifdef CONFIG_ATHR_8033_PHY
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#define is_ar8033() 1
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#else
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#define is_ar8033() 0
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#endif
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#ifdef CONFIG_VIR_PHY
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#define is_vir_phy() 1
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#else
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#define is_vir_phy() 0
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#endif
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#ifdef CFG_ATHRS27_PHY
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#define is_s27() 1
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#else
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#define is_s27() 0
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#endif
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#define ath_arch_init_irq() /* nothing */
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#ifndef __ASSEMBLY__
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int ath_uart_freq(void);
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typedef unsigned int ath_reg_t;
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#if COMPRESSED_UBOOT
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# define prmsg(...)
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#else
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# define prmsg printf
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#endif
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#endif /* __ASSEMBLY__ */
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#define ath_reg_rd(_phys) (*(volatile ath_reg_t *)KSEG1ADDR(_phys))
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#define ath_reg_wr_nf(_phys, _val) \
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((*(volatile ath_reg_t *)KSEG1ADDR(_phys)) = (_val))
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#define ath_reg_wr(_phys, _val) do { \
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ath_reg_wr_nf(_phys, _val); \
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ath_reg_rd(_phys); \
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} while(0)
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#define ath_reg_rmw_set(_reg, _mask) do { \
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ath_reg_wr((_reg), (ath_reg_rd((_reg)) | (_mask))); \
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ath_reg_rd((_reg)); \
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} while(0)
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#define ath_reg_rmw_clear(_reg, _mask) do { \
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ath_reg_wr((_reg), (ath_reg_rd((_reg)) & ~(_mask))); \
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ath_reg_rd((_reg)); \
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} while(0)
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#define ath_uart_rd(y) ath_reg_rd((ATH_UART_BASE+y))
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#define ath_uart_wr(x, z) ath_reg_wr((ATH_UART_BASE+x), z)
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#define REG_OFFSET 4
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#define OFS_RCV_BUFFER (0 * REG_OFFSET)
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#define OFS_TRANS_HOLD (0 * REG_OFFSET)
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#define OFS_SEND_BUFFER (0 * REG_OFFSET)
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#define OFS_INTR_ENABLE (1 * REG_OFFSET)
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#define OFS_INTR_ID (2 * REG_OFFSET)
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#define OFS_DATA_FORMAT (3 * REG_OFFSET)
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#define OFS_LINE_CONTROL (3 * REG_OFFSET)
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#define OFS_MODEM_CONTROL (4 * REG_OFFSET)
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#define OFS_RS232_OUTPUT (4 * REG_OFFSET)
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#define OFS_LINE_STATUS (5 * REG_OFFSET)
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#define OFS_MODEM_STATUS (6 * REG_OFFSET)
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#define OFS_RS232_INPUT (6 * REG_OFFSET)
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#define OFS_SCRATCH_PAD (7 * REG_OFFSET)
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#define OFS_DIVISOR_LSB (0 * REG_OFFSET)
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#define OFS_DIVISOR_MSB (1 * REG_OFFSET)
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/*
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* PLL Config for different CPU/DDR/AHB frequencies
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*/
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#define CFG_PLL_720_600_200 0x01
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#define CFG_PLL_720_680_240 0x02
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#define CFG_PLL_720_600_240 0x03
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#define CFG_PLL_680_680_226 0x04
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#define CFG_PLL_720_600_300 0x05
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#define CFG_PLL_400_400_200 0x06
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#define CFG_PLL_560_450_220 0x07
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#define CFG_PLL_550_400_200 0x08
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#define CFG_PLL_550_600_200 0x09
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#define CFG_PLL_600_600_200 0x0a
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#define CFG_PLL_750_400_250 0x0b
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#define CFG_PLL_800_400_266 0x0c
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#define CFG_PLL_750_667_250 0x0d
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#define CFG_PLL_800_600_266 0x0e
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#define CFG_PLL_800_667_266 0x0f
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#define CFG_PLL_810_700_270 0x10
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#define CFG_PLL_810_666_270 0x11
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#define CFG_PLL_775_650_258 0x12
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#define CFG_PLL_650_400_200 0x13
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#define CFG_PLL_650_600_200 0x14
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#define UBOOT_SIZE (256 * 1024)
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#define PLL_FLASH_ADDR (CFG_FLASH_BASE + UBOOT_SIZE)
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#define PLL_CONFIG_VAL_F (PLL_FLASH_ADDR + CFG_FLASH_SECTOR_SIZE - 0x20)
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#define PLL_MAGIC 0xaabbccdd
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#define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12)
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#define SRIF_PLL_MAGIC 0x73726966 /* srif */
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#include <config.h>
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#if defined(CONFIG_MACH_AR724x)
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# include <724x.h>
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#elif defined(CONFIG_MACH_AR933x)
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# include <933x.h>
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#elif defined(CONFIG_MACH_AR934x)
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# include <934x.h>
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#elif defined(CONFIG_MACH_QCA955x)
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# include <955x.h>
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#elif defined(CONFIG_MACH_QCA953x)
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# include <953x.h>
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#elif defined(CONFIG_MACH_QCA956x)
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# include <956x.h>
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#else
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# error "Building U-Boot for unknown device"
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#endif
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#ifndef __ASSEMBLY__
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#define ATH_MEM_SDRAM 1
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#define ATH_MEM_DDR1 2
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#define ATH_MEM_DDR2 3
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/*
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* GPIO Access & Control
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*/
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void ath_gpio_init(void);
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void ath_gpio_down(void);
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void ath_gpio_up(void);
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void ath_gpio_irq_init(int);
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/*
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* GPIO Helper Functions
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*/
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void ath_gpio_enable_slic(void);
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/* enable UART block, takes away GPIO 10 and 9 */
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void ath_gpio_enable_uart(void);
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/* enable STEREO block, takes away GPIO 11,8,7, and 6 */
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void ath_gpio_enable_stereo(void);
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/* allow CS0/CS1 to be controlled via SPI register, takes away GPIO0/GPIO1 */
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void ath_gpio_enable_spi_cs1_cs0(void);
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/* allow GPIO0/GPIO1 to be used as SCL/SDA for software based i2c */
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void ath_gpio_enable_i2c_on_gpio_0_1(void);
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/*
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* GPIO General Functions
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*/
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void ath_gpio_drive_low(unsigned int mask);
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void ath_gpio_drive_high(unsigned int mask);
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unsigned int ath_gpio_float_high_test(unsigned int mask);
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/* Functions to access SPI through software. Example:
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*
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* ath_spi_down(); ---------------------- disable others from accessing SPI bus taking semaphore
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* ath_spi_enable_soft_access(); -------- disable HW control of SPI
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*
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* <board specific chip select routine>
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*
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* <read/write SPI using using custom routine or general purposeflash routines
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* Custom routine may use:
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*
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* ath_spi_raw_output_u8(unsigned char)
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* ath_spi_raw_output_u32(unsigned int)
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* ath_spi_raw_input_u32()
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*
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* General purpose flash routines:
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* ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len);
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* ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len);
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* ath_spi_flash_sector_erase(unsigned int addr);
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* >
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*
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* <board specific chip deselect routine>
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*
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* ath_spi_disable_soft_acess(); ------- enable HW control of SPI bus
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* ath_spi_up(); ----------------------- enable others to access SPI bus releasing semaphore
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*/
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void ath_spi_init(void);
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void ath_spi_down(void);
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void ath_spi_up(void);
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static inline void
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ath_spi_enable_soft_access(void)
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{
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ath_reg_wr_nf(ATH_SPI_FS, 1);
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}
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static inline void
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ath_spi_disable_soft_access(void)
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{
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ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_DIS);
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ath_reg_wr_nf(ATH_SPI_FS, 0);
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}
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void ath_spi_raw_output_u8(unsigned char val);
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void ath_spi_raw_output_u32(unsigned int val);
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unsigned int ath_spi_raw_input_u8(void);
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unsigned int ath_spi_raw_input_u32(void);
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void ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len);
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void ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len);
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void ath_spi_flash_sector_erase(unsigned int addr);
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/*
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* Allow access to cs0-2 when GPIO Function enables cs0-2 through SPI register.
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*/
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static inline void
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ath_spi_enable_cs0(void)
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{
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unsigned int cs;
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ath_spi_down();
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ath_spi_enable_soft_access();
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cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
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ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_0 | cs);
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}
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static inline void
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ath_spi_enable_cs1(void)
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{
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unsigned int cs;
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#if defined(CONFIG_MACH_AR934x) || \
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defined(CONFIG_MACH_QCA955x)
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ath_spi_down();
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ath_spi_init();
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ath_spi_enable_soft_access();
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cs = ath_reg_rd(ATH_SPI_WRITE) & ATH_SPI_CS_DIS;
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ath_reg_wr_nf(ATH_SPI_WRITE, cs | ATH_SPI_CLK_HIGH);
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cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
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ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs | ATH_SPI_CLK_HIGH);
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ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs);
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#else
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ath_spi_down();
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ath_spi_enable_soft_access();
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cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS;
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ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs);
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#endif
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}
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static inline void
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ath_spi_disable_cs(void)
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{
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unsigned int cs = ath_reg_rd(ATH_SPI_WRITE) | ATH_SPI_CS_DIS;
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ath_reg_wr_nf(ATH_SPI_WRITE, cs);
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ath_spi_disable_soft_access();
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ath_spi_up();
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}
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/*
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* Example usage to access BOOT flash
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*/
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static inline void
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ath_spi_flash_cs0_sector_erase(unsigned int addr)
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{
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ath_spi_enable_cs0();
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ath_spi_flash_sector_erase(addr);
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ath_spi_disable_cs();
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}
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static inline void
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ath_spi_flash_cs0_write_page(unsigned int addr, unsigned char *data, int len)
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{
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ath_spi_enable_cs0();
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ath_spi_flash_write_page(addr, data, len);
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ath_spi_disable_cs();
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ATHEROS_H */
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